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參數資料
型號： TMX320F2810PBKA
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數字信號處理器
文件頁數： 51/103頁
文件大小： 1341K
代理商： TMX320F2810PBKA
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
watchdog block
The watchdog block on the F2810 and F2812 is identical to the one used on the 240x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter.
Figure 11 shows the various functional blocks within the watchdog module.
/512
OSCCLK
WDCR (WDPS(2:0))
WDCLK
WDCNTR(7:0)
WDKEY(7:0)
Bad Key
Good Key
1
0
1
WDCR (WDCHK(2:0))
Bad
WDCHK
Key
WDCR (WDDIS)
Clear Counter
SCSR (WDENINT)
Watchdog
Prescaler
Generate
Output Pulse
(512 OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55 + AA
Key Detector
XRS
XPPLDIS
WDRST
O.C.
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles (similarly for the WDINT signal if enabled).
Figure 11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal is
fed to the LPM block so that it can wake the device from STANDBY (if enabled). Refer to
”
Low-Power Modes
Block
”
section of this data sheet for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE
mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
P
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TMP320F2810PBKA DIGITAL SIGNAL PROCESSORS
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