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參數資料
| 型號： | W26L04AJ-12I |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 144K |
| 代理商： | W26L04AJ-12I |
Preliminary W26L04A
256K
× 16 HIGH-SPEED CMOS STATIC RAM
Publication Release Date: October 1999
- 1 -
Revision A1
GENERAL DESCRIPTION
The W26L04A is a high-speed, low-power CMOS static RAM organized as 262,144
× 16 bits that
operates on a single 3.3-volt power supply.
The W26L04A has an active low chip select, separate upper and lower byte selects, and a fast output
enable. No clock or refreshing is required. Separate byte select controls ( LB and UB ) allow
individual bytes to be written and read. LB controls I/O1-I/O8, the lower byte. UB controls
I/O9
I/O16, the upper byte. This device is well suited for use in high-density, high-speed system
applications.
FEATURES
High speed access time: 10/12 nS (max.)
Low power consumption:
Active: 660 mW (max.)
Single
+3.3V power supply
Fully static operation
No clock or refreshing
Industrial operating temperature grade
available
All inputs and outputs directly TTL compatible
Three-state outputs
Data byte control
LB (I/O1I/O8), UB (I/O9I/O16)
Available packages: 44-pin 400 mil SOJ and
44-pin TSOP(II)
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
VDD
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
NC
I/O9
I/O10
I/O11
I/O12
VDD
VSS
I/O13
I/O14
I/O15
I/O16
LB
UB
OE
A15
A16
A17
44-PIN
BLOCK DIAGRAM
A0
.
A17
I/O1
I/O16
VDD
VSS
.
DATA I/O
DECODER
CONTROL
UB
CS
OE
WE
LB
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
A17
Address Inputs
I/O1
I/O16
Data Inputs/Outputs
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower Byte Select I/O1
I/O8
UB
Upper Byte Select I/O9
I/O16
VDD
Power Supply
VSS
Ground
NC
No Connection
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