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參數資料
型號: XR1005
廠商: MIMIX BROADBAND INC
元件分類: 衰減器
英文描述: 19.0-26.0 GHz GaAs MMIC Receiver
中文描述: RF/MICROWAVE DOWN CONVERTER
封裝: DIE-10
文件頁數: 1/9頁
文件大小: 356K
代理商: XR1005
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Characteristic Data and Specifications are subject to change without notice.
2006 Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
their obligation to be compliant with U.S. Export Laws.
April 2006 - Rev 10-Apr-06
Mimix Broadband
s 19.0-26.0 GHz GaAs MMIC receiver has a noise
figure of 2.5 dB and 20.0 dB image rejection across the band. This
device is a two stage balanced LNA followed by an image reject
sub-harmonic anti-parallel diode mixer and includes an integrated LO
buffer amplifer. The image reject mixer eliminates the need for a
bandpass filter after the LNA to remove thermal noise at the image
frequency. The use of a sub-harmonic mixer makes the provision of
the LO easier than for fundamental mixers at these frequencies. I and Q
mixer outputs are provided and an external 90 degree hybrid is
required to select the desired sideband. This MMIC uses Mimix
Broadband
s 0.15
μ
m GaAs PHEMT device model technology, and is
based upon electron beam lithography to ensure high repeatability
and uniformity. The chip has surface passivation to protect and provide
a rugged part with backside via holes and gold metallization to allow
either a conductive epoxy or eutectic solder die attach process. This
device is well suited for Millimeter-wave Point-to-Point Radio, LMDS,
SATCOM and VSAT applications.
19.0-26.0 GHz GaAs MMIC
Receiver
Page 1 of 9
Sub-harmonic Receiver
Integrated LNA, LO Buffer, Image Reject Mixer
+2.0 dBm LO Drive Level
2.3 dB Noise Figure
20.0 dB Image Rejection
100% On-Wafer RF, DC and Noise Figure Testing
100% Visual Inspection to MIL-STD-883 Method 2010
Features
General Description
Absolute Maximum Ratings
Supply Voltage (Vd)
Supply Current (Id1,Id2)
Gate Bias Voltage (Vg)
Input Power (RF Pin)
Storage Temperature (Tstg)
Operating Temperature (Ta)
Channel Temperature (Tch)
+4.5 VDC
180, 165 mA
+0.3 VDC
0.0 dBm
-65 to +165
O
C
-55 to MTTF Table
MTTF Table
Chip Device Layout
(3) Channel temperature affects a device's MTTF. It is
recommended to keep channel temperature as low as
possible for maximum life.
3
3
Electrical Characteristics (Ambient Temperature T = 25
o
C)
Parameter
Frequency Range (RF) Upper Side Band
Frequency Range (RF) Lower Side Band
Frequency Range (LO)
Frequency Range (IF)
Input Return Loss RF (S11)
3
Small Signal Conversion Gain RF/IF (S21)
2,3
LO Input Drive (P
LO
)
Image Rejection
2,3
Noise Figure (NF)
2,3
Isolation LO/RF @ LOx1/LOx2
Input Third Order Intercept (IIP3)
1,2
Drain Bias Voltage (Vd1)
Drain Bias Voltage (Vd2)
Gate Bias Voltage (Vg1,2)
Supply Current (Id1) (Vd1=3.5V, Vg=-0.3V Typical)
Supply Current (Id2) (Vd2=4.0V,Vg=-0.3V Typical)
(1) Measured using constant current.
(2) Measured using LO Input drive level of +2.0 dBm.
(3) Max and Min are specified for RF=20 to 24 GHz
Units
GHz
GHz
GHz
GHz
dB
dB
dBm
dBc
dB
dB
dBm
VDC
VDC
VDC
mA
mA
Min.
19.0
19.0
8.0
DC
-
7.5
-
15.0
-
-
-
-
-
-1.2
-
-
Typ.
-
-
-
-
20.0
9.5
+2.0
20.0
2.3
65.0
-7.0
+4.0
+4.0
-0.3
130
116
Max.
26.0
26.0
14.5
3.0
-12.0
12.0
-
-
2.9
-
-
+4.5
+4.5
+0.1
155
140
R1005
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