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參數資料
| 型號： | μPA101 |
| 廠商： | NEC Corp. |
| 英文描述： | High Frequency NPN Transistor Array(高頻NPN晶體管陣列) |
| 中文描述： | 高頻NPN晶體管陣列（高頻npn型晶體管陣列） |
| 文件頁數： | 1/8頁 |
| 文件大小： | 61K |
| 代理商： | ΜPA101 |
1995, 1999
DATA SHEET
COMPOUND TRANSISTOR
μ
PA101
FEATURES
BUILT-IN ULTRAHIGH FREQUENCY MULTIPLIER:
(Each Transistor has f
T
9 GHz)
OUTSTANDING h
FE
LINEARITY
TWO PACKAGE OPTIONS:
μ
PA101B:
Superior thermal dissipation due to studded 14-pin ceramic package
μ
PA101G:
Reduced circuit size due to 8-pin plastic SOP package for surface mounting
DESCRIPTION AND APPLICATIONS
This Si bipolar transistor array contains six bipolar transistors which have f
T
9 GHz. Applications include a multiplier,
double balanced mixer, phase detector, or AGC circuit. The two package options offer a choice of excellent heat
dissipation or 35 % size reduction.
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA101B-E1
14-pin ceramic package
μ
PA101G-E1
8-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
SYMBOLS
PARAMETERS
UNITS
RATINGS
V
CBO
*
Collector to Base Voltage
V
15
V
CEO
*
Collector to Emitter Voltage
V
6
V
EBO
*
Emitter to Base Voltage
V
2.5
I
C
*
Collector Current
mA
40
P
T
Power Dissipation
μ
PA101B
μ
PA101G
mW
mW
650
250
T
J
Junction Temperature
μ
PA101B
μ
PA101G
°
C
°
C
200
125
T
STG
Storage Temperature
μ
PA101B
μ
PA101G
°
C
°
C
–55 to +200
–55 to +125
*
Absolute maximum ratings for each transistor.
HIGH FREQUENCY NPN TRANSISTOR ARRAY
Caution electro-static sensitive devices
The mark
shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10706EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
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