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參數資料
型號: μPD4564163
廠商: NEC Corp.
英文描述: 64M-bit Synchronous DRAM(64M同步動態RAM)
中文描述: 6400位同步DRAM(6400同步動態RAM)的
文件頁數: 1/84頁
文件大小: 697K
代理商: ΜPD4564163
The information in this document is subject to change without notice.
1997
MOS INTEGRATED CIRCUIT
μ
PD4564441, 4564841, 4564163 for Rev. E
64M-bit Synchronous DRAM
4-bank, LVTTL
DATA SHEET
Document No. M12621EJ8V0DS00 (8th edition)
Date Published October 1998 NS CP (K)
Printed in Japan
The mark
shows major revised points.
Description
The
μ
PD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304
×
4
×
4, 2,097,152
×
8
×
4, 1,048,576
×
16
×
4 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by A12 and A13 (Bank Select)
Byte control (
×
16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
4,
×
8,
×
16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
相關PDF資料
PDF描述
μPD4564441 64M-bit Synchronous DRAM(64M同步動態RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動態RAM)
μPD4564323 64M-bit Synchronous DRAM(64M 同步動態RAM)
μPD45D128164 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態RAM)
μPD45D128442 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態RAM)
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