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| 型號： | 08F1774 |
| 英文描述： | TRANSISTOR MOSFET TO-220 |
| 中文描述： | 晶體管場效應(yīng)管- 220 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 159K |
| 代理商： | 08F1774 |
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS E-FET.
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
500
Vdc
Drain–Gate Voltage (RGS = 1.0 M)
VDGR
500
Vdc
Gate–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100
°C
— Single Pulse (tp ≤ 10 s)
ID
IDM
1.0
0.8
3.0
Adc
Apk
Total Power Dissipation
Derate above 25
°C
PD
40
0.32
Watts
W/
°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS =10 Vdc, IL = 3.0 Apk, L =10 mH, RG = 25 )
EAS
45
mJ
Thermal Resistance
— Junction to Case
— Junction to Ambient, when surface mounted using minimum recommended pad size
R
θJC
R
θJA
3.13
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Order this document
by MTP1N50E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
MTP1N50E
TMOS POWER FET
1.0 AMPERES
500 VOLTS
RDS(on) = 5.0 OHM
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
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