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參數資料
| 型號： | 100ELT23M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5V Dual Differential PECL to TTL Translator (Preliminary) |
| 中文描述： | DUAL PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 114K |
| 代理商： | 100ELT23M |
Preliminary
2002 Fairchild Semiconductor Corporation
DS500774
www.fairchildsemi.com
September 2002
Revised September 2002
1
100ELT23
5V Dual Differential PECL to TTL Translator (Preliminary)
General Description
The 100ELT23 is a dual differential PECL to TTL translator
operating from a single
+
5V supply.
The dual gate design of the 100ELT23 makes it ideal for
applications which require the translation of a clock and a
data signal.
The 100 series is temperature compensated.
Features
I
Typical propagation delay of 3.5 ns
I
TTL output drive: I
OH
=
24 mA; I
OL
=
3 mA
I
Flow through pinout
I
Q Output will default to a LOW with the inputs left Open
I
Internal pull-down resistors on inputs
I
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
I
Typical I
CCH
of 23 mA, I
CCL
of 26 mA
I
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
I
Moisture Sensitivity Level TBD
I
ESD Performance:
Human Body Model
>
TBD
Machine Model
>
TBD
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Code
Top Mark
KLT23
KT23
Package Description
Package
Number
M08A
MA08D
100ELT23M
100ELT23M8
(Preliminary)
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name
Description
D
0
, D
0
, D
1
, D
1
Q
0
, Q
1
V
CC
GND
PECL Differential Inputs
TTL Outputs
Positive Supply
Ground
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