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參數資料
| 型號： | 1026RI-45TE13 |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | MSOP-8 |
| 文件頁數： | 5/17頁 |
| 文件大?。?/td> | 108K |
| 代理商： | 1026RI-45TE13 |
13
Preliminary Information
CAT1026, CAT1027
Doc No. 3010, Rev. E
Immediate/Current Address Read
The CAT1026 and CAT1027 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=255. The counter will wrap around to Zero and
continue to clock out valid data for the 2K devices. After
the CAT1026 and CAT1027 receive a slave address
(with the R/
W bit set t o one), an acknowledge is issued,
and the requested 8-bit byte is transmitted. The master
device does not send an acknowledge, but will generate
a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1026 and CAT1027
acknowledge, the Master device sends the START
condition and the slave address again, this time with the
R/
W bit set to one. The CAT1026 and CAT1027 then
respond with an acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 send the
inital 8-bit byte requested, the Master responds with an
acknowledge which tells the device it requires more
data. The CAT1026 and CAT1027 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1026
and CAT1027 address bits so that the entire memory
array can be read during one operation.
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 12. Selective Read Timing
Figure 13. Sequential Read Timing
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