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參數資料
| 型號： | 1032EA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:4 RoHS Compliant: Yes |
| 中文描述： | 在系統可編程高密度可編程邏輯器件 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 198K |
| 代理商： | 1032EA |
ispLSI
1032EA
In-System Programmable High Density PLD
1032ea_03
1
Functional Block Diagram
Features
HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1032E
NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems (V
CCIO
Pin)
— Open-Drain Output Option
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
—
f
max
= 200 MHz Maximum Operating Frequency
—
t
pd
= 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Output Routing Pool
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
O
O
CLK
Global Routing Pool (GRP)
0139A/1032EA
Logic
Array
D Q
D Q
D Q
D Q
GLB
Description
The ispLSI 1032EA is a High Density Programmable
Logic Device containing 192 Registers, 64 Universal I/O
pins, four Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032EA features 5V in-system
programmability (ISP
) and in-system diagnostic capa-
bilities via IEEE 1149.1 Test Access Port. The ispLSI
1032EA device offers non-volatile reprogrammability of
the logic, as well as the interconnects to provide truly
reconfigurable systems. A functional superset of the
ispLSI 1032 architecture, the ispLSI 1032EA device adds
user selectable 3.3V or 5V I/O and open-drain output
options.
The basic unit of logic on the ispLSI 1032EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1
…
D7 (Figure 1). There are a total of 32 GLBs in the
ispLSI 1032EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
相關PDF資料 |
PDF描述 |
|---|---|
| 1032E | Shielded Paired Cable; Number of Conductors:50; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:25 RoHS Compliant: Yes |
| 1032 | In-System Programmable High Density PLD |
| 10371QC | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:100ohm RoHS Compliant: Yes |
| 10371QI | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:100ohm RoHS Compliant: Yes |
| 100371 | Low Power Triple 4-Input Multiplexer with Enable(低功耗、帶使能端的四組4輸入多路轉換器) |
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