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參數資料
| 型號： | 11257-816 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Coaxial Cable; Coaxial RG/U Type:178B; Impedance:50ohm; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Material:FEP; Cable/Wire MIL SPEC:M17/169-00001; Jacket Color:White; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 低偏移時鐘扇出緩沖器集成電路 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 386K |
| 代理商： | 11257-816 |
XT
April 1999
Intel and Pentium are registered trademarks of Intel Corporation. I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
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1.0 Features
Generates up to eighteen low-skew, non-inverting
clocks from one clock input
Supports up to four SDRAM DIMMs
Uses either I
2
C
-bus or SMBus serial interface with
Read and Write capability for individual clock output
control
Output enable pin tristates all clock outputs to facili-
tate board testing
Clock outputs skew-matched to less than 250ps
Less than 5ns propagation delay
Output impedance: 17
at 0.5V
DD
Serial interface I/O meet I
2
C specifications; all other
I/O are LVTTL/LVCMOS-compatible
Five differerent pin configurations available:
FS6050: 18 clock outputs in a 48-pin SSOP
FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
FS6053: 13 clock outputs in a 28-pin SOIC
FS6054: 14 clock outputs in a 28-pin SOIC
Figure 1: Block Diagram (FS6050)
Serial
Interface
SDRAM_(0:1)
VDD
SCL
SDA
CLK_IN
OE
FS6050
SDRAM_(2:3)
VSS
VDD
SDRAM_(4:5)
VSS
VDD
SDRAM_(6:7)
VSS
VDD
SDRAM_(8:9)
VSS
VDD
SDRAM_(10:11)
VSS
VDD
SDRAM_(12:13)
VDD
SDRAM_(14:15)
VDD
SDRAM_16
VDD
VSS_I
2
C
VDD_I
2
C
VDD
SDRAM_17
VSS
18
2.0 Description
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium
II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
Under I
2
C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
1
4
2
3
4
5
6
7
8
4
4
4
4
4
4
4
(
(
V
S
S
V
V
S
V
S
S
(
V
(
9
1
1
1
1
1
1
1
S
V
C
V
S
S
V
V
1
1
1
2
2
2
2
S
S
V
V
S
V
V
2
C
4
3
3
3
3
3
3
3
S
S
V
O
S
S
V
V
3
3
3
2
2
2
2
2
C
V
S
V
S
S
V
2
S
2
V
V
FS6050
48-pin SSOP
Figure 3: Pin Configuration (FS6051)
1
2
3
4
5
6
7
8
V
S
S
V
V
S
V
S
S
V
9
1
1
1
1
1
1
1
S
V
C
V
1
1
1
2
2
2
2
S
V
V
2
C
V
O
S
S
V
V
2
2
2
V
2
C
V
S
2
S
2
S
FS6051
28-pin SOIC, SSOP
Additional pin configurations are noted on Page 2.
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