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參數資料
| 型號： | 12H1601-2RD8 |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 50 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE H02, MODULE |
| 文件頁數： | 9/19頁 |
| 文件大小： | 356K |
| 代理商： | 12H1601-2RD8 |
H Series Data Sheet
50 Watt DC-DC Cassette Converters
REV. MAR 27, 2006
Page 17 of 19
www.power-one.com
Formula for additional external input capacitor
2
Po (th + 0.3 ms) 100
Ci ext = ––––––––––––––––––––– - Ci min
η (Vti 2 – Vi min2)
where as:
Ci min = minimum internal capacitance [mF], according to
the table below
Ci ext = external input capacitance [mF]
Po
= output power [W]
η
= efficiency [%]
th
= hold-up time [ms]
Vi min = minimum input voltage [V]
Vti
= threshold level [V]
Remarks: The threshold level
Vti of option V2 and V3 is
adjusted during manufacture to a value according to table
Undervoltage monitor functions, section Option D.
A decoupling diode should be connected in series with the
input to avoid the input capacitance discharging through
other loads connected to the same source voltage.
V ACFAIL signal (VME)
Available for units with
Vo1 =5.1 V.
This option defines an undervoltage monitoring circuit
for the input or the input and main output voltage equivalent
to option D, and generates the ACFAIL signal (V signal)
which conforms to the VME standard. The low state level of
the ACFAIL signal is specified at a sink current of
IV = 48
mA to
VV -0.6 V (open-collector output of a NPN transistor).
The pull-up resistor feeding the open-collector output
should be placed on the VME backplane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time
th of at least 4 ms before the 5.1 V
output drops to 4.875 V when the 5.1 V output is fully
loaded. This hold-up time
th should be provided by an
external input capacitance. Consequently the working input
voltage and the threshold level
Vti should be adequately
above the minimum input voltage
Vi min of the converter so
that enough energy is remaining in this capacitance.
If the input voltage is below the required level, an external
hold-up capacitor (C i ext) should be added.
the monitored voltage(s) exceed(s)
Vt + Vh. The threshold
level
Vt is adjustable by a potentiometer accessible through
a hole in the front cover.
Versions V2 and V3 are available as shown below.
Option V operates independently of the built-in input
undervoltage lockout circuit. A logic "low" signal is
generated at pin 5 as soon as one of the monitored voltages
drops below the preselected threshold level
Vt. The return
for this signal is Vo1– (pin 23). The V output recovers when
Table 18: Available internal input capacitance and factory
potentiometer setting of Vti with resulting hold-up time.
Types
12H
24H
48H
Unit
Ci min
2.2
0.75
0.19
mF
Vt i
9.5
19.5
39
VDC
th
0.19
0.87
0.89
ms
Table 19: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment range
Typical hysteresis
Vh [% of Vt]
(VME compatible)
of threshold level
Vt
for Vt min to Vt max
Vi
Vo1
Vti
Vto
Vhi
Vho
V2
yes
no
Vi min to Vi max 1–
3.0 to 0.5
–
V3
yes
Vi min to Vi max 1
0.95 to 0.98
Vo1 2
3.0 to 0.5
"0"
1 Threshold level adjustable by potentiometer (not recommended for mobile applications)
2 Fixed value between 95% and 98% of Vo1 (tracking), output undervoltage monitoring is not a requirement of VME standard
V output (V2, V3):
Connector pin V is internally connected to the open
collector of an NPN transistor. The emitter is connected to
the negative potential of output 1.
VV
≤ 0.6 V (logic low)
corresponds to a monitored voltage level (
Vi and/or Vo1) <
Vt. The current IV through the open collector should not
exceed 50 mA. The NPN output is not protected against
external overvoltages.
VV should not exceed 80 V.
Vi, Vo1 status
V output,
UV
Vi or Vo1 < Vt
low, L,
VV
≤ 0.6 V at IV = 50 mA
Vi and Vo1 > Vt + Vh
high, H,
IV
≤ 25 A at VV = 5.1 V
Fig. 19
Output configuration of options V2 and V3
Formula for threshold level for desired value of
th:
2
Po (th + 0.3 ms) 100
V ti =
–––––––––––––––––––––– +
Vi min2
Ci min
η
Vo1+
Vo1–
V
VV
IV
Rp
Input
11009
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