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參數資料
| 型號： | 16864 |
| 英文描述： | Board Layout Considerations for PDR & PDT ? 21.3KB (PDF) |
| 中文描述： | 板布局注意事項民主共和國 |
| 文件頁數： | 1/3頁 |
| 文件大小： | 21K |
| 代理商： | 16864 |
Publication#
16864
Issue Date:
April 1992
Rev.
A
Amendment
/0
Board Layout Considerations
for Am79865 and Am79866
Application Note
by Michael Bray
Advanced
Micro
Devices
The Physical Data Transmitter (PDT) and Physical Data
Receiver (PDR) contain high frequency analog Phase
Lock Loops (PLLs). Reliable operation in a high fre-
quency analog and digital environment requires that
some simple board layout rules be followed.
For example, most high speed applications which are
laid out on a wire wrap board will not work reliably. Be-
cause they have at most one power and ground plane,
most wire wrap cards have insufficient separation be-
tween small signal current and digital switching current.
Digital switching noise can couple into the analog PLL,
causing phase errors and loss of synchronization. The
preferred realization of a high speed application is on a
printed circuit board, where the user can control the lay-
out of power and ground planes.
Another source of information on board layout tech-
niques is AMD publication #16356A, “High-Speed-
Board Design Techniques”.
GENERAL BOARD LAYOUT GUIDELINES
1. Use a PC board with separate GND and V
CC
planes.
Ensure that the connection between each supply pin
and the corresponding power/ground plane is as
short as possible (not more than 1/4 inch).
2. Use two capacitors which differ by at least a factor of
ten in value to decouple the PDT/PDR chips. The re-
actance of large capacitors has a significant induc-
tive component at high frequencies. Because of this
inductive component, a single large capacitor is not
very effective against high frequency noise. Two ca-
pacitors, one typically of 1
μ
F and one of 0.1
μ
F are
more efficient at decoupling than a single large ca-
pacitor of 1.1
μ
F. The recommended layout is as
shown in Figure 1.
3. Keep all bypass capacitors as close to the power
pins of the device as possible. Lead lengths should
be minimized.
4. Use high quality RF grade capacitors, such as type
COG or X7R. The use of type Z5U capacitors is not
recommended.
C1, C2
C3
V
CC1
14
V
CC1
17
GND1
16
V
CC2
7
GND2
4
C1, C2
C1, C2
A
B
Leads must
be very
short (<1/4
″
)
Am79865
PDT
C3
V
CC1
20
GND2
2
V
CC2
16
GND2
6
C1, C2
C
D
Am79866
PDR
V
CC
Plane
GND Plane
GND2
17
V
CC
Plane
GND Plane
C1 = 0.1
μ
F (ceramic)
C2 = 0.047
μ
F (ceramic)
C3 = 1
μ
F (tantalum)
To further decouple the power supplies, ferrite beads may be used at locations A, B, C, and D.
16864A-001A
C1 C2
Figure 1. PDT/R Decoupling Layouts
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