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| 型號： | 19195 |
| 英文描述： | Microprocessor Family Phase Lock Loop (PLL) Clock Control Application Note Microprocessor Family Clock Gating Recommendations Application Note |
| 中文描述： | 微處理器家族鎖相環（PLL）的時鐘控制應用指南系列微處理器時鐘門控建議書的說明 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 109K |
| 代理商： | 19195 |
Publication #:
19195
Rev.
C
Amendment/
0
Issue Date:
August 1995
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Advanced
Micro
Devices
Clock Gating Recommendations
Application Note
Microprocessor motherboard design requires that special attention be paid to the design of the clock control circuitry.
A designer must provide for timing control of the clock at startup. Keeping this requirement in mind, this application
note provides three examples of clock delay circuits.
AMD recommends that the CLK input to an Am486
or
Am5
X
86 microprocessor be grounded until V
CC
has
reached its normal operating level. Once V
CC
reaches
its normal operating level, the CPU is able to receive its
specified clock frequency.
Methods of gating the CPU clock include:
I
Using a chipset that does not clock the CPU until
V
CC
has fully ramped.
I
Using a clock driver with an output enable.
I
Using a clock clamping circuit to gate the CPU clock.
For proper operation of Am486 and Am5
X
86 devices,
the system timing must be maintained as illustrated in
Figure 1. Good design practice dictates gating or “hold-
ing off” the CPU clock until the system V
CC
has reached
its normal operating voltage. The timing diagram illus-
trates that once V
CC
reaches its operating voltage point
(either 3.3 V or 5 V), and the PWRGOOD signal is active,
RESET must be asserted for at least 1 ms to allow the
CPUs internal PLL to lock prior to system operation.
Chipset with Internal Delay
Because many 486 core logic chipsets use PWRGOOD
and CLK as inputs to generate RESET and CPUCLK
as outputs, they have the potential to incorporate an
internal delay function, holding off the CPU until V
CC
has
reached it’s normal operating voltage.
Figure 2 illustrates a chipset capable of providing inter-
nal clock gating.
Figure 2.
Internal Delay Function of Chipset
Note:
Check your chipset’s data sheet for specifics on
your chipset’s internal delay function.
Figure 1.
Timing Diagram of PicoPower Redwood Chipset Delay Function
Chipset
CLK
CPUCLK
RESET
PWRGOOD
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