
Publication#
18498
Issue Date:
May 1994
Rev.
A
Amendment
/0
PCMCIA Socket Interface Controller for the
Am29200 Microcontroller Family
Application Note
by Mark McClain and David Stoenner
Advanced
Micro
Devices
This application note defines a simple, small, low-cost hardware interface to a PCMCIA PC Card
socket from an Am29200 microcontroller family member.
OVERVIEW
This application note presents the hardware imple-
mentation of an interface between an Advanced Micro
Devices Am29200 microcontroller family member and a
Personal Computer Memory Card International
Association (PCMCIA) PC Card Standard (Release 2.0)
socket. This design is intended for use with any of the
following microcontrollers: Am29200, Am29205 ,
Am29240 , Am29243 , Am29245 , and future mem-
bers of the Am29200 microcontroller family that share
signal or pinout compatibility with these processors.
One card socket is supported. The required integrated
circuit hardware consists of one 8-bit register, three 8-bit
buffers, two 8-bit transceivers, and control logic imple-
mented by one MACH 215 Programmable Logic De-
vice (PLD).
All of the signal definitions and design discussions in this
application note are with reference to the September
1991 PCMCIA PC Card Standard Release 2.0. A copy
of this specification may be obtained from the PCMCIA
located at 1030B East Duane Ave. Suite G, Sunnyvale
CA 94086, (408) 720–0107.
FUNCTIONAL DESCRIPTION
Schematics
As shown in the two schematic pages in Appendix A, the
PC Card socket is isolated from the processor system by
three 74LS244 address buffers (U1, U2, and U3) and
two 74LS245 data transceivers (U6 and U7), so that a
card may be inserted or removed during system opera-
tion without disturbing the system address and data
buses.
The PC card address space is divided into a series of
2-Mbyte pages. Pages are selected by the upper ad-
dress bits loaded into the 74LS374 page address regis-
ter (U5).
The PCMCIA PC Card socket is shown as J1.
The +12-V Vpp voltage pins of the socket may be con-
nected to the +12-V supply via a discrete pass-transistor
switch provided by Q1 and Q2. The diode D1 holds the
Q1 emitter one diode voltage drop above ground so that
in order to turn on, the base of Q1 must be driven by a
voltage greater than the sum of the Q1 base emitter volt-
age drop, plus the diode voltage drop. This keeps the
turn-on voltage for Q1 well above the voltage level for a
TTL Low, which ensures Q1 stays off until a TTL High
level is driven on the Vpp_EN signal. Whenever Q2 is
off, the Vpp pins are held at the Vcc voltage through re-
sistor R10 as required by the PC Card specification.
The control logic is provided by a MACH215 PLD (U4)
device, which integrates the equivalent of four 22RA8
Programmable Array Logic, CMOS Electrically-eras-
able (PAL CE) devices into a single 44-pin PLCC pack-
age.
Control Logic
The PC Card socket control logic implemented by the
MACH215 device contains a control register, used by
the processor to manage the different modes of opera-
tion, and a status register, where the current state of the
socket can be monitored. These two registers are se-
lected by address lines A23–A21, as defined by the ad-
dress map described on page 3. A read within the
register address range returns the status register con-
tents on the I/D7–I/D0 bus lines, and a write loads all bits
of the control register from the I/D7–I/D0 bus lines. Thus
the status register is read-only and the control register is
write-only. Software must maintain a copy of the control
register if its current state must be known in order to
modify some control bits without changing others.
Control Register
The control register bits are assigned as follows:
Control[7]: PC Card enable
Control[6]: Not used
Control[5]: Vpp (+12 V) enable
Control[4]: Disable wait-state generator
Control[3]: Status change (STSCHG) interrupt en-
able
Control[2]: 0=16-bit wide card mode; 1=8-bit wide
card mode
Control[1]: PC Card reset
Control[0]: 0=Memory Card mode; 1=I/O Card mode