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參數(shù)資料
| 型號： | 20747 |
| 英文描述： | Using a PCMCIA Card as a Boot ROM on an ?lanSC300 Microcontroller Design ?lanSC300/?lanSC310 ISA Bus Anomalies |
| 中文描述： | 以此為啟動ROM上？lanSC300微控制器設(shè)計？lanSC300 /？lanSC310 ISA總線異常一個PCMCIA卡 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 38K |
| 代理商： | 20747 |
Publication#
20747
Issue Date: October
1996
Rev:
A
Amendment/
0
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
élan
SC300 and
élan
SC310 Devices’
ISA Bus Anomalies
Application Note
The élanSC300 and élanSC310 microcontrollers’ ISA bus has several anomalies that should be
accounted for when designing a system with ISA devices. It is fairly simple to design around these
issues, and none of them should stop the designer from using the ISA bus. ROM access using
ROMCS and DOSCS are also discussed here since they are affected by some of the ISA anomalies.
ISA CLOCK SPEED
The ISA cycles are timed from a 9.2 MHz clock, which
is slightly faster than a typical ISA bus clock (about
8.3 MHz). Therefore, the ISA cycles generated by the
élanSC300 and SC310 microcontrollers will be slightly
faster than typical ISA cycles.
FAST ROM CYCLE ISSUES
The ROM can be accessed either at slow (ISA bus)
speeds or fast (CPU clock) speeds by setting the bits at
Index registers B3H and B8H. The slow cycles use the
9.2 MHz ISA clock and are compatible with ISA timings.
The fast cycles use the CPU clock, which can be as
fast as 33 MHz. These fast ROM cycles violate the ISA
timing specification. This faster-than-ISA cycle is bene-
ficial for system performance and is acceptable to the
ROM device since the designer can use very fast ROM
and Flash chips (70 nsec or faster parts).
A problem can occur with fast ROM cycles since the
ROM shares signals with the ISA bus. The Address
Bus (SA23:0), Data Bus (SD15:0), Commands (MEMR
and MEMW), and 16-bit signal (MEMCS16) are used
by both the ROM and ISA devices.
Designers should be aware of the following issues and
avoid them in their system designs.
Fast Commands Seen On The ISA Bus
ROM uses the ISA bus commands (MEMR and
MEMW). In Fast mode, they occur faster than ISA tim-
ings allow. The designer should take care that any ISA
devices in the design will not have a problem with these
fast commands. Note that the ISA device will not be ac-
cessed with the fast commands, it will merely see them
occur during the ROM access.
MEMCS16 Return Time
MEMCS16 is the signal that an ISA device can assert
to signal to the élanSC300 and SC310 devices that it
can be accessed with a 16-bit data bus instead of the
default 8-bit one. The élanSC300 and SC310 micro-
controllers use MEMCS16 for ISA cycles as well as for
ROMCS and DOSCS accesses. When MEMCS16 is
generated, the élanSC300 and SC310 devices will
allow a 16-bit cycle. SBHE and SA0 are decoded by
the target device to determine which bytes of the data
bus are active.
For DOSCS, there is an alternate way to access the
ROM with a 16-bit cycle. Setting index register 51H bit
1 will force all accesses to the DOSCS signal to occur
with a 16-bit data bus, and MEMCS16 does not need to
be asserted. There is no alternate method of accessing
the ROMCS signal at 16 bit.
When operating at a fast speed, both the ROMCS and
DOSCS signals need MEMCS16 to return within 10
nsec after the chip selects are generated inside the
élanSC300 and SC310 devices. Due to pin delay
times, it may be necessary to return MEMCS16 before
the SA signals come out of the chip. Since this is not
possible, it is recommended not to allow 16-bit
accesses to ROMCS if it is programmed for fast ac-
cess. Fast cycles to DOSCS can still be used as a 16-
bit access if they are set with the register (Index 51H
bit 1) and not by MEMCS16.
Summary:
Do not do fast ROMCS or DOSCS ac-
cesses at 16 bit if relying on the MEMCS16 signal
being returned. Only use slow ROMCS or DOSCS with
MEMCS16. The design can still use fast DOSCS at 16
bit if it is implemented using the Index register instead
of MEMCS16.
MEMCS16 and IOCS16 Hold Time
The MEMCS16 and/or IOCS16 hold time becomes an
issue when using an ISA device that does 16-bit mem-
ory or I/O transfers and the system does 8-bit fast ROM
cycles. The problem is that the MEMCS16 and/or
IOCS16 signal may still be asserted by the ISA device
at the beginning of the ROM access, and the chip will
try to do a 16-bit access to a ROM that should be 8-bit.
Since the ROM access is timed off the CPU clock, it
can start one CPU clock after the end of a valid 16-bit
ISA access. At a 33 MHz CPU clock rate, this is less
than 30 nsec (because of pad delays getting the sig-
nals off chip), which is less than the ISA spec. If
MEMCS16 and/or IOCS16 is still asserted at a low
level by the ISA device when the ROM access starts,
the ROM access will be 16 bit.
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