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| 型號： | 23380A |
| 英文描述： | SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF) |
| 中文描述： | SDRAM的性能監視器的？蘭？SC520微控制器？ 233KB（PDF格式） |
| 文件頁數： | 1/18頁 |
| 文件大小： | 233K |
| 代理商： | 23380A |
Publication#
23380
Issue Date:
April 2000
Rev:
A
Amendment/
0
Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
SDRAM Performance Monitors with the
élanSC520 Microcontroller
Application Note
by Daniel Mann and James Magro
This application note describes the concept, design considerations, functions, and use of the
SDRAM performance monitors
with the élanSC520 microcontroller.
OVERVIEW
The élanSC520 microcontroller includes two non-
intrusive Adaptive Digital Element (ADDIE)
performance monitor resources for monitoring a variety
of SDRAM controller parameters. Features of the
performance monitors include:
I
Non-intrusive (hardware)
I
Probability resolution of 0.39%
I
Less than 4% error
I
Monitoring of the following SDRAM controller pa-
rameters:
– Write buffer hits (implying merge or collapse)
– Read merge hits (from the write buffer)
– Write buffer full occurrence
– Read buffer hits
– SDRAM page and bank misses
I
Two ADDIE resources that can be configured to
concurrently monitor any two SDRAM controller
parameters
Registers
The ADDIE performance monitors are controlled by the
performance monitor control registers, as shown in
Table 1.
Refer to Appendix A, “SDRAM Performance Monitor
Registers” for more information about the performance
monitor registers.
Table 1.
Performance Monitor Control Registers (Memory Mapped)
Register Name
MMCR Offset
Address
Function
Performance Monitor Control
44h
Selects parameter to monitor for both ADDIE 0 and
ADDIE 1.
Performance Monitor Data 0
48h
Returns ADDIE 0 performance data.
Performance Monitor Data 1
49h
Returns ADDIE 1 performance data.
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