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參數資料
| 型號： | 28C256TRPFB-15 |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | PROM |
| 英文描述： | 256K EEPROM (32K x 8-Bit) EEPROM |
| 中文描述： | 32K X 8 EEPROM 5V, 150 ns, DFP28 |
| 封裝： | DFP-28 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 283K |
| 代理商： | 28C256TRPFB-15 |
1
M
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301- wwwmaxwell.com
256K EEPROM(32K x 8-Bit)
28C256T
2001 Maxwell Technologies
All rights reserved.
EEPROM
02.18.02 Rev 5
F
EATURES
:
R
AD
-P
AK
radiation-hardened against natural space radia-
tion
Total dose hardness:
- > 100 Krad (Si), dependent upon space mssion
Excellent Single Event Effects:
- SEL
TH
LET: > 120 MeV/mg/cm
2
- SEU
TH
LET (read mode): > 90 MeV/mg/cm
2
- SEU
TH
LET (write mode): > 18 MeV/mg/cm
2
Package:
- 28 pin R
AD
-P
AK
flat pack
- 28 pin R
AD
-P
AK
DIP
- JEDEC approved byte wide pinout
High Speed:
- 120, 150 ns maximumaccess times available
High endurance:
- 10,000 erase/write (in Page Mode), 10-year data
retention
Page Write Mode:
- 1 to 64 bytes
Low power dissipation:
- 15 mA active current (cycle = 1 μs)
- 20 μA standby current (CE = V
CC
)
D
ESCRIPTION
:
Maxwell Technologies’ 28C256T high density 256k-bit
EEPROMmcrocircuit features a greater than 100 krad (Si)
total dose tolerance, depending upon space mssion. The
28C256T is capable of in-systemelectrical byte and page pro-
grammability. It has a 64-Byte page programmng function to
make its erase and write operations faster. It also features
data polling to indicate the completion of erase and program-
mng operations.
Maxwell Technologies' patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the mcrocircuit pack-
age. It elimnates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mssion. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
OE, C E, and WE
LOGIC
Y DEC ODER
X DEC ODER
DATA LATC H
INPUT/OUTPUT
BUFFERS
Y-GATING
C ELL MATRIX
IDENTIFIC ATION
OE
WE
C E
ADDRESS
INPUTS
V
C C
GND
DATA INPUTS/OUTPUTS
I/O0 - I/O7
Logic Diagram
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