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參數資料
| 型號： | 28LV64A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64K (8K x 8) Low Voltage CMOS EEPROM(低壓,64K位, CMOS 并行EEPROM) |
| 中文描述： | 64K的（8K的× 8）低電壓的CMOS EEPROM的（低壓，64K的位，并行的CMOS EEPROM的） |
| 文件頁數： | 1/8頁 |
| 文件大小： | 65K |
| 代理商： | 28LV64A |
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 1
FEATURES
2.7V to 3.6V Supply
Read Access Time—300 ns
CMOS Technology for Low Power Dissipation
- 8 mA Active
- 50
μ
A CMOS Standby Current
Byte Write Time—3 ms
Data Retention >200 years
High Endurance - Minimum 100,000 Erase/Write
Cycles
Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
Electronic Signature for Device Identification
Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
- 28-pin Very Small Outline Package (VSOP)
8x13.4mm
Available for Extended Temperature Ranges:
- Commercial: 0C to +70C
- Industrial: -40C to +85C
DESCRIPTION
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte
write”, the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in ‘wired-or’ systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
PACKAGE TYPES
BLOCK DIAGRAM
OE
A11
A9
A8
NC
WE
Vcc
RDY/BSY
A12
A7
A6
A5
A4
A3
A10
CE
I/07
I/06
I/05
I/04
I/03
Vss
I/02
I/01
I/00
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
21
20
19
18
17
16
15
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
14
13
12
11
10
9
8
OE
A11
A9
A8
NC
WE
CC
22
23
24
25
26
27
28
RDY/V
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
Pin 1 indicator on PLCC on top of package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
Vcc
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A
4
A
3
R
2
N
1
V
3
W
3
N
3
I
I
V
N
I
I
I
1
1
1
1
1
1
2
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
D
P
T
V
64K bit
Cell Matrix
Y Gating
Input/Output
Buffers
Data
Poll
DaCircuitry
Chip Enable/
Output Enable
Control Logic
AutTiming
PrGeneration
Y
Decoder
X
Decoder
L
a
t
c
h
e
s
A0
I
A12
I
I
I
I
I
I
I
I
I
I
VCC
VSS
CE
OE
WE
Rdy/
I/O0...................I/O7
28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
This document was created with FrameMaker 4 0 4
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