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參數資料
| 型號： | 29F52 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit Registered Transceiver(8位寄存器式收發器) |
| 中文描述： | 8位注冊收發器（8位寄存器式收發器） |
| 文件頁數： | 1/8頁 |
| 文件大小： | 79K |
| 代理商： | 29F52 |
2000 Fairchild Semiconductor Corporation
DS009606
www.fairchildsemi.com
April 1988
Revised September 2000
2
29F52
29F53
8-Bit Registered Transceiver
General Description
The 29F52 and 29F53 are 8-bit registered transceivers.
Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Separate clock,
clock enable and 3-STATE output enable signals are pro-
vided for each register. The A
0
–A
7
output pins are guaran-
teed to sink 24 mA while the B
0
–B
7
output pins are
designed for 64 mA.
The 29F53 is an inverting option of the 29F52. Both trans-
ceivers are AMD Am2952/2953 functional equivalents.
Features
I
8-bit registered transceivers
I
Separate clock, clock enable and 3-STATE output
enable provided for each register
I
AMD Am2952/2953 functional equivalents
I
Both inverting and non-inverting options available
I
24-Pin slimline package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Logic Symbols
29F52
IEEE/IEC
29F52
29F53
IEEE/IEC
29F53
Order Number
29F52SC
29F52SPC
29F53SPC
Package Number
M24B
N24C
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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PDF描述 |
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| 29F53 | 8-Bit Registered Transceiver(8位寄存器式收發器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 29F52 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 29F524DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| 29F524DM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| 29F524LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| 29F524PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
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