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參數資料
| 型號： | 2SD1363 |
| 英文描述： | Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay |
| 中文描述： | 晶體管|晶體管|叩| 50V五（巴西）總裁| 7A條一（c）|至220VAR |
| 文件頁數： | 1/3頁 |
| 文件大小： | 51K |
| 代理商： | 2SD1363 |
1
Transistor
2SD1302
Silicon NPN epitaxial planer type
For low-voltage output amplification
For muting
For DC-DC converter
I
Features
G
Low collector to emitter saturation voltage V
CE(sat)
.
G
Low ON resistance R
on
.
G
High foward current transfer ratio h
FE
.
I
Absolute Maximum Ratings
(Ta=25C)
Unit: mm
Parameter
Collector to base voltage
Collector to emitter voltage
Emitter to base voltage
Peak collector current
Collector current
Collector power dissipation
Junction temperature
Storage temperature
1:Emitter
2:Collector
3:Base
JEDEC:TO–92
EIAJ:SC–43A
5.0
±
0.2
4.0
±
0.2
5
±
0
1
±
0
0.45
+0.2
0.45
+0.2
1.27
1.27
2
±
0
2.54
±
0.15
2
1
3
Symbol
V
CBO
V
CEO
V
EBO
I
CP
I
C
P
C
T
j
T
stg
Ratings
25
20
12
1
0.5
600
150
–55 ~ +150
Unit
V
V
V
A
A
mW
C
C
I
Electrical Characteristics
(Ta=25C)
Parameter
Collector cutoff current
Collector to base voltage
Collector to emitter voltage
Emitter to base voltage
Forward current transfer ratio
Collector to emitter saturation voltage
Base to emitter saturation voltage
Transition frequency
Collector output capacitance
ON resistanse
Symbol
I
CBO
V
CBO
V
CEO
V
EBO
h
FE1*1
h
FE2
V
CE(sat)
V
BE(sat)
f
T
C
ob
R
on*3
Conditions
V
CB
= 25V, I
E
= 0
I
C
= 10
μ
A, I
E
= 0
I
C
= 1mA, I
B
= 0
I
E
= 10
μ
A, I
C
= 0
V
CE
= 2V, I
C
= 0.5A
*2
V
CE
= 2V, I
C
= 1A
*2
I
C
= 0.5A, I
B
= 20mA
I
C
= 0.5A, I
B
= 50mA
V
CB
= 10V, I
E
= –50mA, f = 200MHz
V
CB
= 10V, I
E
= 0, f = 1MHz
min
25
20
12
200
60
typ
0.13
200
10
1.0
max
100
800
0.4
1.2
Unit
nA
V
V
V
V
V
MHz
pF
*1
h
FE1
Rank classification
Rank
R
S
T
h
FE1
200 ~ 350
300 ~ 500
400 ~ 800
*2
Pulse measurement
*3
R
on
Measurement circuit
V
B
I
B
=1mA
R
on
= V
1000(
)
A
–V
B
f=1kHz
V=0.3V
1k
V
A
V
V
V
B
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| 2SD1366AB | Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay |
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