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參數資料
| 型號： | 3D7205K-25 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Lens; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 整體式5 - TAP在固定延遲線 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 256K |
| 代理商： | 3D7205K-25 |
3D7205
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7205)
FEATURES
All-silicon, low-power CMOS
technology
TTL/CMOS compatible
inputs and outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
8 through 500ns
Delay tolerance:
5% or 2ns
Temperature stability:
±
3% typical (0C-70C)
Vdd stability:
±
2% typical (4.75V-5.25V)
Minimum input pulse width:
20% of total delay
14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines
FUNCTIONAL DESCRIPTION
The 3D7205 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 8.0ns through 100ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7205 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7205 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-
insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PACKAGES
1
2
3
4
8
7
6
5
IN
O2
O4
GND
VDD
O1
O3
O5
3D7205Z
SOIC
(150 Mil)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
N/C
N/C
O2
N/C
O4
N/C
GND
VDD
N/C
N/C
O1
N/C
O3
N/C
O5
3D7205S SOL
(300 Mil)
8
7
6
5
1
2
3
4
IN
O2
O4
GND
VDD
O1
O3
O5
3D7205M DIP
3D7205H Gull-Wing
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
N/C
O2
N/C
O4
GND
VDD
N/C
O1
N/C
O3
N/C
O5
3D7205
3D7205G Gull-Wing
3D7205K Unused pins
removed
DIP
here.
For package marking details, click
.PIN DESCRIPTIONS
IN
Delay Line Input
O1
Tap 1 Output (20%)
O2
Tap 2 Output (40%)
O3
Tap 3 Output (60%)
O4
Tap 4 Output (80%)
O5
Tap 5 Output (100%)
VDD +5 Volts
GND Ground
N/C
No Connection
PART NUMBER
SOIC-8
3D7205Z
TOLERANCES
TOTAL
DELAY (ns)
INPUT RESTRICTIONS
Absolute
Max
Oper. Freq.
DIP-8
3D7205M
3D7205H
DIP-14
3D7205
3D7205
G
3D7205K
-8
-10
-15
-20
-25
-30
-50
-75
-100
SOIC-16
3D7205S
TAP-TAP
DELAY
(ns)
Max
Operating
Frequency
Min
Operating
Pulse Width
Absolute
Min
Oper. P.W.
-8
-10
-15
-20
-25
-30
-50
-75
-100
-8
-10
-15
-20
-25
-30
-50
-75
-100
-8
-10
-15
-20
-25
-30
-50
-75
-100
40.0
±
2.0
50.0
±
2.5
75.0
±
3.8
100
±
5.0
125
±
6.3
150
±
7.5
250
±
12.5
375
±
18.8
500
±
25.0
8.0
±
1.5
10.0
±
2.0
15.0
±
2.3
20.0
±
2.5
25.0
±
2.5
30.0
±
3.0
50.0
±
5.0
75.0
±
7.5
100
±
10.0
9.52 MHz
6.67 MHz
4.44 MHz
3.33 MHz
2.66 MHz
2.22 MHz
1.33 MHz
0.89 MHz
0.67 MHz
71.4 MHz
50.0 MHz
33.3 MHz
25.0 MHz
20.0 MHz
16.7 MHz
10.0 MHz
6.67 MHz
5.00 MHz
52.5 ns
75.0 ns
113 ns
150 ns
188 ns
225 ns
375 ns
563 ns
750 ns
7.0 ns
10.0 ns
15.0 ns
20.0 ns
25.0 ns
30.0 ns
50.0 ns
75.0 ns
100.0 ns
Doc #96007
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
相關PDF資料 |
PDF描述 |
|---|---|
| 3D7205K-30 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205K-50 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205S-15 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205S-20 | MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205S-25 | MONOLITHIC 5-TAP FIXED DELAY LINE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 3D7205K30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7205K-30 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205K50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7205K-50 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE |
| 3D7205K75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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