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參數(shù)資料
| 型號(hào)： | 41LV16100B-60KLI |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 100萬(wàn)× 16（16兆）動(dòng)態(tài)與江戶頁(yè)面模式內(nèi)存 |
| 文件頁(yè)數(shù)： | 17/22頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | 41LV16100B-60KLI |
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IS41LV16100B
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
ISSI
Functional Description
The IS41LV16100B is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(
RAS). The column address is latched by the Column
Address Strobe (
CAS). RAS is used to latch the first nine bits
and
CAS is used to latch the latter nine bits.
The IS41LV16100B has two
CAS controls, LCAS and UCAS.
The
LCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single
CAS input on
the other 1M x 16 DRAMs. The key difference is that each
CAS
controls its corresponding I/O tristate logic (in conjunction with
OE and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41LV16100B
CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two
CAS controls give the
IS41LV16100B both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it is
terminated by returning both
RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS or OE,
whichever occurs last, while holding
WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS or WE, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
with
RAS at least once every 128 ms. Any read, write, read-
modify-write or
RAS-onlycyclerefreshestheaddressedrow.
2. Using a
CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding
CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VDD supply, an initial pause of
200 s is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS signal).
During power-on, it is recommended that
RAS track with
VDD or be held at a valid VIH to avoid current surges.
相關(guān)PDF資料 |
PDF描述 |
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| 41LV16100B-60KL | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60K | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TI | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TLI | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TL | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 41LV16100B-60T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41LV16100B-60TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 41MB2-EXT | 制造商:Leviton Manufacturing Co 功能描述: |
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