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參數(shù)資料
| 型號(hào)： | AD7888AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 164K |
| 代理商： | AD7888AR |
REV. 0
AD7888
–14–
MICROPROCESSOR INTERFACING
The serial interface on the AD7888 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7888 with some of the
more common microcontroller and DSP serial interface protocols.
AD7888 to TMS320C5x
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7888.
The
CS
input allows easy interfacing with an inverter between
the serial clock of the TMS320C5x and the AD7888 being the
only glue logic required. The serial port of the TMS320C5x is
set up to operate in burst mode with internal CLKX (TX serial
clock) and FSX (TX frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM
= 1 and TXM = 1. The connection diagram is shown in Figure 17.
AD7888*
DOUT
DIN
SCLK
CS
TMS320C5x*
CLKX
*ADDITIONAL PINS OMITTED FOR CLARITY
CLKR
DR
DT
FSX
FSR
Figure 17. Interfacing to the TMS320C5x
AD7888 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced to the AD7888
with an inverter between the serial clock of the ADSP-21xx
and the AD7888. This is the only glue logic required. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 18. The ADSP-
21xx has the TFS and RFS of the SPORT tied together with
TFS set as an output and RFS set as in input. The DSP oper-
ated in Alternate Framing Mode and the SPORT Control Reg-
ister is set up as described. The frame synchronization signal
generated on the TFS is tied to
CS
and, as with all signal pro-
cessing applications, equidistant sampling is necessary. How-
ever, in this example the timer interrupt is used to control the
sampling rate of the ADC and, under certain conditions, equi-
distant sampling may not be achieved.
The Timer Registers, etc., are loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and hence
the reading of data. The frequency of the serial clock is set in
the SCLKDIV Register. When the instruction to transmit with
TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted or it may
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV Register is loaded with the value 3, a
SCLK of 2 MHz is obtained, and eight master clock periods will
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, then 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. The
situation will result in nonequidistant sampling as the transmit
instruction is occurring on a SCLK edge. If the number of SCLKs
between interrupts is not a figure of N.5, equidistant sampling
will be implemented by the DSP.
AD7888*
DOUT
DIN
SCLK
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
SCLK
DR
DT
RFS
TFS
ADSP-21xx*
Figure 18. Interfacing to the ADSP-21xx
AD7888 to DSP56xxx
The connection diagram in Figure 19 shows how the AD7888
can be connected to the SSI (Synchronous Serial Interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is oper-
ated in synchronous mode (SYN bit in CRB = 1) with inter-
nally generated 1-bit clock period frame sync for both TX and
RX (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An in-
verter is also necessary between the SCLK from the DSP56xxx
and the SCLK pin of the AD7888 as shown in Figure 19.
DOUT
DIN
SCLK
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
DSP56xxx*
SCK
AD7888*
SRD
STD
SC2
Figure 19. Interfacing to the DSP56xxx
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| AD7888AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 125ksps 12-bit Serial 16-Pin SOIC N T/R |
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| AD7888ARU | 功能描述:IC ADC 12BIT 8CH 125KSPS 16TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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