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參數資料
| 型號： | 48SD6404 |
| 廠商： | Maxwell Technologies, Inc |
| 英文描述： | CAP 2.2UF 50V CERAMIC MONO 20% |
| 中文描述： | 256 MB的SDRAM的16梅格× 4位× 4，銀行 |
| 文件頁數： | 40/42頁 |
| 文件大小： | 596K |
| 代理商： | 48SD6404 |
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48SD6404
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All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
Pin Functions:
CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS (INPUT PIN): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operations section.
A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY9, A11) is determined by A0 to A9, A11 level at
the read or write command cycle CLK rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks
are pre-charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
BA0/BA1 (BS) is pre charged. For details refer to the command operation section.
BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 48SD6404 is divided
into bank 0, bank 1, bank 2 and bank 3. The 48SD6404 contains 8192-row X 2048-column X 4-bit. If BA0
and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and
BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode,
clock suspend mode and self refresh mode.1
DQM (INPUT PIN): DQM control input/output buffers
Read operation: If DQM is High, the output buffer becomes High-Z. If the DQM is Low, the output buffer
becomes Low-Z. ( The latency of DQM during reading is 2 clock cycles.)
Write operation: If DQM is High, the previous data is held ( the new data is not written). If the DQM is Low,
the data is written. ( The latency of DQM during writing is 0 clock cycles.)
DQ0 TO DQ3 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ3).
V
CC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output
buffer.)
V
SS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.
1. Self Refresh should only be used at temperatures below 70 °C
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相關代理商/技術參數 |
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| 48SD6404RPFE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
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