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參數(shù)資料
| 型號： | 497AE |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | 測試/ JTAG支持|的CMOS | SOJ | 28腳|塑料 |
| 文件頁數(shù)： | 1/92頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | 497AE |
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User Manual
April 2001
497AE and 1215E Boundary-Scan Master 2
Advanced Operational Mode
Features
s
The BSM2 is available in 2 versions:
— The 497AE is available in a 28-pin SOJ pack-
age
— The 1215E device is available in a 48-pin TQFP
package
s
The 497AE and 1215E differ in the following capa-
bilities
— 497AE has an 8-bit data-bus and no user I/O
signals
— 1215E has a 16-bit data-bus and 3 user I/O sig-
nals
s
Selectable between two operational modes:
— 497AA compatibility
— Advanced Operational Mode (497AE)
s
3.3 V power supply, but fully 5 V (TTL) tolerant for
all inputs and outputs
s
Dedicated 8 kbits test data in (TDI) and test data
out (TDO) buffers; FIFO or fully addressable
s
Simple and flexible host interface options:
— 497AE, synchronous or asynchronous 8-bit
data bus
— 1215E, 16-bit asynchronous data bus for maxi-
mum throughput
s
Self-timing interface to a microprocessor/micro-
controller
s
Automatic test mode select (TMS) sequence gen-
eration
s
Programmable test clock (TCK) generator with
gated TCK mode
s
Provides test reset (TRST*) optional TAP signal
s
External pin control to 3-state test access port
(TAP) signals (1215E)
s
Conflict-free automatic test pattern generator
(ATPG)
s
32-bit signature analysis register (SAR) with
response masking for repeatable signatures
s
TCK output frequency of 65 MHz
s
Maskable processor interrupts; no lockup condition
s
Built-in self-test for >95% fault coverage
s
Support protocols for multidrop backplane test
configurations, such as
TI’s1 addressable scan
port protocol
s
Provides retiming (pipeline) delays of up to 13 TCK
cycles to correct skewing
s
One general-purpose input, two general-purpose
outputs. Outputs can be programmed for use as
DMA control signals (1215E device only).
Description
The Agere Systems Inc. 497AE/1215E Boundary-
Scan Master 2 (BSM2) communicates with a generic
processor in parallel and controls the test and diag-
nosis (T&D) of a unit under test (UUT), which could
be a device, board, or system, based on the ANSI/
IEEE 2 standard 1149.1-1990 TAP and Boundary-
Scan (B-S) Architecture. It serializes test vectors,
delivers them to the UUT using the standard proto-
col, and stores the UUT response as raw data or as a
signature. An ATPG generates four common test
sequences for interconnect test, cluster test, etc. The
device also solves the potential problems of bus con-
flict and nonrepeatable board-level signatures asso-
ciated with the B/S architecture. Finally, the BSM2
provides support for edge-connector/backplane test
and system test and diagnosis.
The BSM2 comes in two package sizes. The 497AE
is a 3.3 V, 28-pin SOJ package that provides both
software and hardware backward compatibility to the
497AA BSM. The 1215E is a 3.3 V, 48-pin TQFP
package with a 16-bit data bus and direct register
access.
Manual Description
This manual describes the advanced operational
modes of the 497AE and 1215E devices. The 1215E
device offers higher throughput, using a 16-bit data-
bus, and 3 user I/O signals. For additional informa-
tion, contact your Agere Account Manager.
*
Asterisk on any pin name indicates active-low.
1.
TI is a registered trademark of Texas Instruments Inc.
2.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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