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參數資料
| 型號： | 5241 |
| 元件分類： | 數字電位計 |
| 英文描述： | Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface |
| 中文描述： | 四數字可編程電位計（民進黨⑩）與64個龍頭和2線接口 |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 111K |
| 代理商： | 5241 |
1
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
CAT5241
Quad Digitally Programmable Potentiometers (DPP)
with 64 Taps and 2-wire Interface
FEATURES
I
Four linear-taper digitally programmable
potentiometers
I
64 resistor taps per potentiometer
I
End to end resistance 2.5k
, 10k
, 50k
or 100k
I
Potentiometer control and memory access via
2-wire interface (I
2
C like)
I
Low wiper resistance, typically 80
I
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
I
Automatic recall of saved wiper settings at
power up
I
2.5 to 6.0 volt operation
I
Standby current less than 1
μ
A
I
1,000,000 nonvolatile WRITE cycles
I
100 year nonvolatile memory data retention
I
20-lead SOIC and TSSOP packages
I
Industrial temperature range
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2011, Rev. J
registers is via a 2-wire serial bus (I
2
C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
RH0
W0
W2
W3
W1
H2
H3
RH1
R
R
RL0
L2
L3
RL1
R
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
SCL
SDA
A0
A1
A2
A3
R
R
R
R
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CAT
5241
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
SOIC Package (J, W)
TSSOP Package (U, Y)
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