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參數(shù)資料
| 型號(hào)： | 533FBFREQDGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 225K |
| 代理商： | 533FBFREQDGR |
Rev. 1.1 6/07
Copyright 2007 by Silicon Laboratories
Si533
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Applications
Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si533
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is
required for each output frequency, the Si533 uses one fixed crystal to
provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si533 IC based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
2 selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pin 1 output enable (OE)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
Clock
Synthesis
VDD
CLK+
CLK–
OE
GND
FS
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
Si5602
1
2
3
6
5
4
GND
FS
VDD
CLK+
CLK–
OE
1
2
3
6
5
4
GND
FS
VDD
CLK+
NC
OE
LVDS/LVPECL/CML
CMOS
REVISION D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 533FC000286DG | 制造商:Silicon Laboratories Inc 功能描述:DUAL XO 6 PIN 0.3PS RS JTR |
| 533FC000308DG | 制造商:Silicon Laboratories Inc 功能描述:DUAL XO 6 PIN 0.3PS RS JTR |
| 533FC000339DG | 制造商:Silicon Laboratories Inc 功能描述:DUAL XO 6 PIN 0.3PS RS JTR |
| 533HC000620DG | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 DUAL XO 6 PIN 0.3PS RS JTR RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| 533JNM | 制造商: 功能描述: 制造商:undefined 功能描述: |
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