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參數資料
| 型號： | 533JBFREQDG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 533JBFREQDG |
Rev. 1.1 6/07
Copyright 2007 by Silicon Laboratories
Si533
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Applications
Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si533
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is
required for each output frequency, the Si533 uses one fixed crystal to
provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si533 IC based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
2 selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pin 1 output enable (OE)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
Clock
Synthesis
VDD
CLK+
CLK–
OE
GND
FS
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
Si5602
1
2
3
6
5
4
GND
FS
VDD
CLK+
CLK–
OE
1
2
3
6
5
4
GND
FS
VDD
CLK+
NC
OE
LVDS/LVPECL/CML
CMOS
REVISION D
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