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參數資料
| 型號： | 5476 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 108K |
| 代理商： | 5476 |
TL/F/6528
5
w
June 1989
5476/DM5476/DM7476
Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the nega-
tive transition of the clock, the data from the master is trans-
ferred to the slave. The logic state of J and K inputs must
not be allowed to change while the clock is high. The data is
transfered to the outputs on the falling edge of the clock
pulse. A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs.
Features
Y
Alternate Military/Aerospace device (5476) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6528–1
Order Number 5476DMQB, 5476FMQB,
DM5476J, DM5476W or DM7476N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs
Outputs
PR
CLR
CLK
J
K
Q
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
L
L
H
H
H
L
H
*
Q
0
H
L
L
H
H
*
Q
0
L
H
é
é
é
é
Toggle
H
e
High Logic Level
L
e
Low Logic Level
X
e
Either Low or High Logic Level
é
e
Positive pulse data. The J and K inputs must be held constant while
the clock is high. Data is transfered to the outputs on the falling edge of the
clock pulse.
*
e
This configuration is nonstable; that is, it will not persist when the preset
and/or clear inputs return to their inactive (high) level.
Q
0
e
The output logic level before the indicated input conditions were es-
tablished.
Toggle
e
Each output changes to the complement of its previous level on
each complete active high level clock pulse.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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