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參數資料
| 型號： | 54AC109F |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 觸發器 |
| 英文描述： | CABLE ASSEMBLY; LEAD-FREE SOLDER; 10-32 MALE TO 10-32 MALE RIGHT ANGLE; 50 OHM, RG178B/U COAX |
| 中文描述： | 雙JK上升沿觸發器 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 167K |
| 代理商： | 54AC109F |
54AC109
54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to S
D (Set) sets Q to HIGH level
LOW input to C
D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D and SD makes both Q and Q
HIGH
Features
n ICC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
Pin Names
Description
J
1,J2,K1,K2
Data Inputs
CP
1,CP2
Clock Pulse Inputs
C
D1,CD2
Direct Clear Inputs
S
D1,SD2
Direct Set Inputs
Q
1,Q2,Q1,Q2
Outputs
FACT is a registered trademark of Fairchild Semiconductor Corporation.
DS100267-1
DS100267-2
IEEE/IEC
DS100267-7
August 1998
54AC109
54ACT109
Dual
JK
Positive
Edge-T
riggered
Flip-Flop
1998 National Semiconductor Corporation
DS100267
www.national.com
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| 54AC109L | Dual JK Positive Edge-Triggered Flip-Flop |
| 54AC10 | Triple 3-Input NAND Gate |
| 54AC10D | Triple 3-Input NAND Gate |
| 54AC10F | Triple 3-Input NAND Gate |
| 54AC10L | Triple 3-Input NAND Gate |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 54AC109FM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 54AC109FMQB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 54AC109L | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual JK Positive Edge-Triggered Flip-Flop |
| 54AC109LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 54AC109LMQB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
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