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參數資料
| 型號： | 54FCT162511ATPVGB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發器 |
| 英文描述： | FCT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | GREEN, SSOP-56 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 107K |
| 代理商： | 54FCT162511ATPVGB |
1
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SEPTEMBER 2009
IDT54/74FCT162511AT/CT
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
DESCRIPTION:
The FCT162511T 16-bit registered/latched transceiver with parity is built
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checkerintheA-to-BdirectionandaparitycheckerintheB-to-Adirection. Error
checkingisdoneatthebytelevelwithseparateparitybitsforeachbyte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
whichcanbetiedtogetherand/ortiedwithflagsfromotherdevicestoformasingle
error flag or interrupt. The parity error flags are enabled by the
OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
The control pins LEAB, CLKAB, and
OEAB control operation in the A-to-B
direction while LEBA, CLKBA, and
OEBA control the B-to-A direction. GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
incheckingmode. TheODD/
EVENselectiscommonbetweenthetwodirections.
Except for the ODD/
EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
GEN/CHK
Latch/
Register
Byte
Parity
Generator/
Checker
Latch/
Register
Byte
Parity
Checking
B0-15
A0-15
PA1,2
PB1,2
PERB
LEAB
CLKAB
OEAB
OEBA
PERA
LEBA
CLKBA
Parity, data
Parity, Data
Data
(Open Drain)
Parity
ODD/EVEN
16
18
2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-2916/4
FEATURES:
0.5 MICRON CMOS Technology
Typical tsk(o) (Output Skew) < 250ps, clocked mode
Low input and output leakage
≤≤≤≤≤1A (max)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 5V ±10%
Balanced Output Drivers:
– ±24mA (industrial)
– ±16mA (military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
FUNCTIONAL BLOCK DIAGRAM
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