- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄34467 > 550CE094M000DGR (SILICON LABORATORIES) VCXO, CLOCK, 94 MHz, CMOS OUTPUT PDF資料下載
參數(shù)資料
| 型號： | 550CE094M000DGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 94 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 550CE094M000DGR |
Rev. 0.6 6/07
Copyright 2007 by Silicon Laboratories
Si550
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
Applications
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory-configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating the long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 to 945 MHz
and selected frequencies to
1.4 GHz
3rd generation DSPLL with
superior jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
Clock Synthesis
ADC
VDD
CLK+
CLK–
Vc
OE
GND
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
Si550
REVISION D
相關PDF資料 |
PDF描述 |
|---|---|
| 550BJ025M000DG | VCXO, CLOCK, 25 MHz, LVDS OUTPUT |
| 550PC040M0096DGR | VCXO, CLOCK, 40.0096 MHz, CMOS OUTPUT |
| 550CJ074M250DG | VCXO, CLOCK, 74.25 MHz, CMOS OUTPUT |
| 550CK029M500DGR | VCXO, CLOCK, 29.5 MHz, CMOS OUTPUT |
| 550FF622M080DGR | VCXO, CLOCK, 622.08 MHz, LVDS OUTPUT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 550CE1112 | 制造商:Cornell Dubilier Electronics 功能描述: |
| 550CE11M2896DG | 功能描述:VCXO振蕩器 SNGL VCXO 6 PIN 7mm x 5mm RoHS:否 制造商:Fox 封裝 / 箱體:5 mm x 3.2 mm 頻率:19.2 Mhz 頻率穩(wěn)定性:2.5 PPM 輸出格式: 封裝:Reel 電源電壓:3 V 端接類型:SMD/SMT 尺寸:3.2 mm W x 5 mm L x 1.5 mm H 最小工作溫度:- 20 C 最大工作溫度:+ 75 C |
| 550CE122M880DG | 功能描述:VCXO振蕩器 SNGL VCXO 6 PIN 7mm x 5mm RoHS:否 制造商:Fox 封裝 / 箱體:5 mm x 3.2 mm 頻率:19.2 Mhz 頻率穩(wěn)定性:2.5 PPM 輸出格式: 封裝:Reel 電源電壓:3 V 端接類型:SMD/SMT 尺寸:3.2 mm W x 5 mm L x 1.5 mm H 最小工作溫度:- 20 C 最大工作溫度:+ 75 C |
| 550CE1231 | 功能描述:鋁質電解電容器-螺旋式接線端 1000UF RoHS:否 制造商:Cornell Dubilier 電容:2400 uF 容差:- 10 %, + 50 % 電壓額定值:450 V ESR:38 mOhms 工作溫度范圍:- 40 C to + 85 C 系列:CGS 直徑:76 mm (3 in) 長度:143 mm (5.625 in) 引線間隔:31.75 mm (1.25 in) 產(chǎn)品:Computer Grade Electrolytic Capacitors |
| 550CE1232 | 功能描述:鋁質電解電容器-螺旋式接線端 4700UF 500V RoHS:否 制造商:Cornell Dubilier 電容:2400 uF 容差:- 10 %, + 50 % 電壓額定值:450 V ESR:38 mOhms 工作溫度范圍:- 40 C to + 85 C 系列:CGS 直徑:76 mm (3 in) 長度:143 mm (5.625 in) 引線間隔:31.75 mm (1.25 in) 產(chǎn)品:Computer Grade Electrolytic Capacitors |
發(fā)布緊急采購，3分鐘左右您將得到回復。