欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào)： 552CE000180BGR
廠商： SILICON LABORATORIES
元件分類： XO, clock
英文描述： VCXO, CLOCK, 54 MHz, CMOS OUTPUT
封裝： ROHS COMPLIANT, SMD, 6 PIN
文件頁(yè)數(shù)： 1/80頁(yè)
文件大小： 3734K
代理商： 552CE000180BGR
Rev. 0.5 7/06
Copyright 2006 by Silicon Laboratories
Si552
DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
Features
Applications
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL, LVDS
& CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical Modules
Clock and data recovery
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
Clock Synthesis
VDD
CLK+
CLK-
VC
GND
FS
ADC
Ordering Information:
Pin Assignments:
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
FS
VDD
CLK+
CLK–
相關(guān)PDF資料
PDF描述
552EC000267BGR VCXO, CLOCK, 100 MHz, LVPECL OUTPUT
552FC000109BG VCXO, CLOCK, 74.25 MHz, LVDS OUTPUT
550CC38M7853BGR VCXO, CLOCK, 38.7853 MHz, CMOS OUTPUT
550CE25M0000BGR VCXO, CLOCK, 25 MHz, CMOS OUTPUT
550AA104M000BGR VCXO, CLOCK, 104 MHz, LVPECL OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
552CE000270DG 制造商:Silicon Laboratories Inc 功能描述:
552CE622M080BG 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
552CE622M080BGR 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
552CF000118DG 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 74.175824MHZ/74.25MHZ VCXO CMOS 6PIN - Trays
552CF000118DGR 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 74.175824MHZ/74.25MHZ VCXO CMOS 6PIN - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 平武县| 秭归县| 宁安市| 合肥市| 精河县| 静乐县| 富川| 台南市| 文昌市| 和平县| 建湖县| 江孜县| 土默特右旗| 尼玛县| 松溪县| 靖边县| 双辽市| 惠州市| 刚察县| 洛宁县| 克拉玛依市| 乐安县| 定日县| 大理市| 宁夏| 藁城市| 平湖市| 安徽省| 项城市| 宁陵县| 东阿县| 金华市| 高邑县| 美姑县| 开平市| 孙吴县| 沙雅县| 阳谷县| 贞丰县| 芦溪县| 镇巴县|