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參數資料
| 型號： | 554AE000237BGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 400 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT, SMD, 8 PIN |
| 文件頁數： | 1/115頁 |
| 文件大小： | 3254K |
| 代理商： | 554AE000237BGR |
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Rev. 0.5 7/06
Copyright 2006 by Silicon Laboratories
Si554
QUAD FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
Features
Applications
Description
The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXOs where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
Four selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL, LVDS
& CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Clock and data recovery
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
Clock Synthesis
ADC
VDD
CLK+
CLK-
Vc
OE
GND
FS1
FS0
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
FS[1]
FS[0]
8
7
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