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參數資料
型號: 5962-005401-QXX
廠商: E2V TECHNOLOGIES PLC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 25 MHz, RISC PROCESSOR, PQFP256
封裝: MQFP-256
文件頁數: 1/42頁
文件大小: 2561K
代理商: 5962-005401-QXX
Rev. 4118F–AERO–04/02
1
Features
Integer Unit Based on SPARC V7 High-performance RISC Architecture
Optimized Integrated 32/64-bit Floating-point Unit
On-chip Peripherals:
– EDAC and Parity Generator and Checker
– Memory Interface:
Chip Select Generator
Waitstate Generation
Memory Protection
–DMA Arbiter
–Timers:
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
– Interrupt Controller With 5 External Inputs
– General Purpose Interface (GPI)
– Dual UART
Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
Fully Static Design
Performance: 20 MIPs/5 MFlops (double precision) at SYSCLK = 25 MHz
Core Consumption: 1.0W typ. at 20 MIPs/0.7W typ. at 10 MIPs
Operating Range: 4.5V to 5.5V (3.3V Capability) -55
°Cto+125°C
Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si)
SEU Event Rate Better than 1E-8 Error/Component/Day (Worst Case)
Latch-up Immunity Better than (LET) 100 MeV-cm2/mg
Quality Grades: ESA SCC, QML Q or V
Package: 256 MQFPF; Bare Die
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 m radiation tolerant (
≥ 300
KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for opti-
mized power consumption. It has been specially designed for space, as it has on-chip
concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
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參數描述
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