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參數(shù)資料
| 型號： | 5962-8687701QPA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 比較器 |
| 英文描述： | COMPARATOR, 4000 uV OFFSET-MAX, 200 ns RESPONSE TIME, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 7/34頁 |
| 文件大小： | 1020K |
| 代理商： | 5962-8687701QPA |
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DC DELTA Parameters
SMD 5962R0052402
(Note 14)
The following conditions apply, unless otherwise specified. V
CC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Symbol
Parameter
Conditions
Notes
Min
Max
Unit
Sub-
groups
V
IO
Input Offset Voltage
V
I = 0V, RS = 50
-0.5
0.5
mV
1
+V
CC = 29.5V, -VCC = -0.5V,
V
I = 0V, VCM = -14.5V,
R
S = 50
-0.5
0.5
mV
1
+V
CC = 2V, -VCC = -28V,
V
I = 0V, VCM = +13V,
R
S = 50
-0.5
0.5
mV
1
±I
IB
Input Bias Current
V
I = 0V, RS = 50K
-12.5
12.5
nA
1
+V
CC = 29.5V, -VCC = -0.5V,
V
I = 0V, VCM = -14.5V,
R
S = 50K
-12.5
12.5
nA
1
+V
CC = 2V, -VCC = -28V,
V
I = 0V, VCM = +13V,
R
S = 50K
-12.5
12.5
nA
1
I
CEX
Output Leakage Current
+V
CC = 18V, -VCC = -18V,
V
O = 32V
-5.0
5.0
nA
1
Post Radiation Parameters
SMD 5962R0052402
(Note 14)
The following conditions apply, unless otherwise specified
Symbol
Parameter
Conditions
Notes
Min
Max
Unit
Sub-
groups
I
IOR
Raised Input Offset Current
V
I = 0V, RS = 50K
(Note 15)
100 +100
nA
1
±I
IB
Input Bias Current
V
I = 0V, RS = 50K
180
0.1
nA
1
+V
CC = 29.5V, VCC = 0.5V, VI =
0V, V
CM = 14.5V, RS = 50K
225
0.1
nA
1
I
CEX
Output Leakage Current
+V
CC = 18V, VCC = 18V,
V
O = 32V
1.0
+25
nA
1
Note 2:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3:
This rating applies for ±15V supplies. The positive input voltage limits is 30 V above the negative supply. The negative input voltage limits is equal to the
negative supply voltage or 30V below the positive supply, whichever is less.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and T
A (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 5:
Human body model, 1.5 k
Ω in series with 100 pF.
Note 6:
Datalog reading in K=V/mV.
Note 7:
Pin names based on an 8 pin package configuration. When using higher pin count packages then:
Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is
Balance / Strobe, Pin 7 is Output, and Pin 8 is V+. For example:
V
56is the Voltage between the Balance and Balance / Strobe pins
Note 8:
I
ST = 2mA at 55°C
Note 9:
Calculated parameter.
Note 10:
Actual min. limit used is 5mA due to test setup.
Note 11:
V
ID is voltage difference between inputs.
Note 12:
Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.
Note 13:
Group A sample ONLY
Note 14:
Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition
D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
Note 15:
Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +V
CC.
15
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