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參數(shù)資料
型號(hào): 5962-8770204RA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP20
封裝: CERAMIC, DIP-20
文件頁(yè)數(shù): 8/10頁(yè)
文件大小: 166K
代理商: 5962-8770204RA
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Chip Information
PROCESS: BiCMOS
MAX4684/MAX4685
0.5
Ω
Ω/0.8Ω
Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
_______________________________________________________________________________________
7
tr < 5ns
tf < 5ns
50%
VIL
LOGIC
INPUT
RL
50
Ω
COM_
GND
IN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VN_
(
RL
)
RL + RON
VIN_
VIH
tOFF
0
NO_
OR NC
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
35pF
V+
VOUT
MAX4684
MAX4685
Figure 2. Switching Time
Test Circuits/Timing Diagrams
50%
VIH
VIL
LOGIC
INPUT
VOUT
0.9 x VOUT
tD
LOGIC
INPUT
RL
50
Ω
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
VOUT
V+
CL
35pF
VN_
COM_
MAX4684
MAX4685
Figure 3. Break-Before-Make Interval
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