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參數(shù)資料
| 型號(hào)： | 5962-9089401MEA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 測(cè)量放大器 |
| 英文描述： | INSTRUMENTATION AMPLIFIER, 500 uV OFFSET-MAX, 4 MHz BAND WIDTH, CDIP16 |
| 封裝： | HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-16 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 464K |
| 代理商： | 5962-9089401MEA |
AD526
REV. D
–10–
GROUNDING AND BYPASSING
Proper signal and grounding techniques must be applied in
board layout so that specified performance levels of precision
data acquisition components, such as the AD526, are not
degraded.
As is shown in Figure 37, logic and signal grounds should be
separate. By connecting the signal source ground locally to the
AD526 analog ground Pins 5 and 6, gain accuracy of the
AD526 is maintained. This ground connection should not be
corrupted by currents associated with other elements within the
system.
GAIN
NETWORK
LATCHES AND LOGIC
DIGITAL
GROUND
AMP
VOUT
FORCE
VOUT
SENSE
ANALOG
GROUND 1
ANALOG
GROUND 2
+VS
–VS
AD526
VIN
+15V
–15V
0.1 F
1 F
+5V
AD574
12-BIT
A/D
CONVERTER
Figure 37. Grounding and Bypassing
OUT
FORCE
OUT
SENSE
0.1 F
–VS
0.1 F
+VS
+5V
A2
A1
A0
VIN
CLK
16
15
14
13
12
11
10
9
12
34
56
78
+
–
AD526
16
84
21
GAIN NETWORK
A1
A0
CS CLK
A2
B
LOGIC AND LATCHES
OUT
FORCE
OUT
SENSE
VOUT
0.1 F
–VS
0.1 F
+VS
+5V
16
15
14
13
12
11
10
9
12
34
56
78
+
–
AD526
16
84
21
GAIN NETWORK
A1
A0
CS CLK
A2
B
LOGIC AND LATCHES
Figure 38. Cascaded Operation
Utilizing the force and sense outputs of the AD526, as shown in
Figure 38, avoids signal drops along etch runs to low impedance
loads.
Table II. Logic Table for Figure 38
VOUT/VIN
A2
A1
A0
10
0
20
0
1
40
1
0
80
1
16
1
0
32
1
0
1
64
1
0
128
1
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