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參數資料
| 型號： | 5962F0323601QXX |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 STANDARD SRAM, 15 ns, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 297K |
| 代理商： | 5962F0323601QXX |
1
FEATURES
15ns maximum access time
Asynchronous operation, functionally compatible with
industry-standard 128K x 32 SRAMs
CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
Radiation performance
- Total-dose: 300 Krad(Si)
- SEL Immune: >100 MeV-cm2/mg
- LETth (0.25): 53.0 MeV-cm
2/mg
- Memory Cell Saturated Cross Section: 1.67E-7cm2/bit
- Neutron Fluence: 3.0E14n/cm2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
Packaging options:
- 68-lead ceramic quad flatpack (9.204 grams with
leadframe
Standard Microcircuit Drawing 5962-03236
- QML compliant part
INTRODUCTION
The UT8R128K32 is a high-performance CMOS static RAM
organized as 131,072 words by 32 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)
is then written into the location specified on the address pins
(A0 through A16). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
Figure 1. UT8R128K32 SRAM Block Diagram
Memory Array
256K x 16
Pre-Charge Circuit
Column Select
Ro
w
Se
le
ct
A1
A2
A4
A5
A6
A7
A8
A9
Data Control
I/O Circuit
Data Control
A10 A11 A12 A13A14 A15
DQ(15) to DQ(0)
DQ(31) to DQ(16)
E1
HHWE
W
E2
LHWE
G
A0
A16
Low Word
Read Circuit
High Word
Read Circuit
A3
Standard Products
UT8R128K32 128K x 32 SRAM
Data Sheet
April, 2005
www.aeroflex.com/4MSRAM
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