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參數資料
| 型號： | 5962F9563003VYC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28 |
| 封裝： | CERAMIC, DFP-28 |
| 文件頁數： | 4/7頁 |
| 文件大小： | 214K |
| 代理商： | 5962F9563003VYC |
HS-1840ARH, HS-1840BRH
4
FN4355.3
September 14, 2010
Burn-In/Life Test Circuits
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
Irradiation Circuit
HS-1840ARH, HS-1840BRH
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
R
GND
+VS
R
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F4
F3
F1
F5
F2
-VS
NOTE:
VS+ = +15.5V ±0.5V, VS- = -15.5V ±0.5V.
R = 1k
Ω ±5%.
C1 = C2 = 0.01F ±10%, 1 EACH PER SOCKET, MINIMUM.
D1 = D2 = 1N4002, 1 EACH PER BOARD, MINIMUM.
INPUT SIGNALS:
SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK
±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
R
GND
VR
+VS
R
-VS
NOTE:
R = 1k
Ω ±5%, 1/4W.
C1 = C2 = 0.01F MINIMUM, 1 EACH PER SOCKET, MINIMUM.
VS+ = 15.5V ±0.5V, VS- = -15.5V ±0.5V, VR = 15.5 ±0.5V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1kΩ
+15V
+1V
+5V
NC
-15V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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