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參數(shù)資料
型號： 5962F9855202VXC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
封裝： CERAMIC, PGA-144
文件頁數(shù)： 1/64頁
文件大小： 1464K
代理商： 5962F9855202VXC
Standard Products
UT69R000 RadHard MicroController
Data Sheet
October 2005
Harvard architecture
-
64K data space
-
1M instruction space
High throughput engine
-
2 clocks per instruction
-
8 MIPS @ 16 MHz
-
Static design
15 levels of interrupts
-
8 external user defined interrupts
-
Machine error and power fail
Two on-board 16-bit interval timers
-
Timer A, 10
s/bit
-
Timer B, 100
s/bit resolution
8-bit software controlled output discrete bus
Register- oriented architecture has 21
user-accessible registers
-
16-bit or 32-bit register configurations
Supports direct memory access (DMA) system
configuration
Built-in 9600 baud UART
Full military operating temperature range, -55oC to
+125oC, in accordance with MIL-PRF-38535 for Class Q
or V
Typical radiation performance:
-
Total dose: 1.0E6 rads(Si)
-
SEL Immune >100 MeV-cm2/mg
-
LETTH(0.25) = 60 MeV-cm
2/mg
-
Saturated Cross Section (cm2) per bit, 1.2E-7
- 2.3E-11 errors/bit-day, Adams to 90%
geosynchronous heavy ion
Post-radiation AC/DC performance characteristics
guaranteed by MIL-STD-883 Method 1019 testing
at 1.0E6 rads(Si)
Latchup immune 1.5-micron CMOS, epitaxial,
double-level-metal technology
Packaging options:
-
132-lead flatpack
-
144-pin pingrid array (plus one index pin)
32
Figure 1. UT69R000 Functional Block Diagram
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
NUI3
STATE1
DI1
DI2
INSTRUCTION
DATA
INSTRUCTION
ADDRESS
MCHNE1
BTERR
MCHNE2
MPROT
PFAIL
INT5
INT6
INT0-4
MRST
20
16
32
ADD
MUX
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
PROCESSOR
CONTROL
LOGIC
OSCILLATOR
/CLOCK
GENERAL
PURPOSE
REGISTERS
OSCIN
OSCOUT
SYSCLK
ID
IC/ICs
ACC
SHIFT REG
TEMP DEST
32
TEMP SRC
BIT REG
32
A MUX
B MUX
32-BIT ALU
16
32
16
ADDR
MUX
BUS
CONTROL
UART
TBR
RBR
TIMCLK
TES
T
UARTOUT
UARTIN
TR
TB
IM
FR
PI
ST
SW
16
5
16
8
OD(7:0)
OPERAND
DATA
DTACK
M/IO
R/WR
DS
OPERAND
ADDRESS
PIPELINE
I/O
MUX
INTER-
RUPTS
16
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