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參數資料
| 型號： | 5962H0153702QXA |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | QUAD 2-CHANNEL, CROSS POINT SWITCH, DFP64 |
| 封裝： | DFP-64 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 81K |
| 代理商： | 5962H0153702QXA |
1
FEATURES
q 400.0 Mbps low jitter fully differential data path
q 200MHz clock channel
q 3.3 V power supply
q 10mA LVDS output drivers
q Input receiver fail-safe
q Cold sparing all pins
q Output channel-to-channel skew is 120ps max
q Configurable as quad 2:1 mux, 1:2 demux, repeater or1:2
signal splitter
q Fast propagation delay of 3.5ns max
q Receiver input threshold < + 100 mV
q Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
q Packaging options:
- 64-lead flatpack
q Standard Microcircuit Drawing 5962-01537
- QML Q and V compliant part
q Compatible with ANSI/TIA/EIA 644-1995 LVDS
Standard
INTRODUCTION
The UT54LVDM228 is a quad 2x2 crosspoint switch utilizing
Low Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The non-blocking design allows connection of
any input to any output or outputs on each switch. LVDS I/O
enable high speed data transmission for point-to point or multi-
drop interconnects. This device can be used as a high speed
differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter. The mux and demux functions are useful for
switching between primary and backup circuits in fault tolerant
systems. The 1:2 signal splitter and 2:1 mux functions are useful
for distribution of a bus across several rack-mounted
backplanes.
The individual LVDS outputs can be put into Tri-State by use
of the enable pins.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
Standard Products
UT54LVDM228 Quad 2x2 400 Mbps Crosspoint Switch
Advanced Data Sheet
March 13, 2002
Figure 1a. UT54LVDM228 Crosspoint Switch Block Diagram
(Partial - see Page 2 for complete diagram)
Out1+
En1
In1+
+
-
1
0
1
0
Out 2+
Sel1
En2
In2+
Sel2
+
-
In1-
Out1-
Out 2-
In2-
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