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參數資料
| 型號： | 5962R1023704QXC |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28 |
| 封裝： | CERAMIC, FLATPACK-28 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 326K |
| 代理商： | 5962R1023704QXC |
1
16FEATURES
16-to-1 Analog Mux
100
Ω Signal paths (typical)
5V single analog supply
Rail-to-Rail signal handling
Asynchronous RESET input
SPI/QSPI and MICROWIREcompatible serial
interface (UT16MX117)
Asynchronous parallel input Interface (UT16MX116)
LVCMOS or CMOS compatible inputs (set by voltage of
VDD_IO pin)
2kV ESD Protection (per MIL-STD-883, Method 3015.7)
Operational environment:
- Total ionizing dose: 300 krad(Si)
- SEL immune to a LET of 110 MeV-cm2/mg
- SEU immune to a LET of 91 MeV-cm2/mg
Packaging: 28 Lead Ceramic Flatpack
Standard Microcircuit Drawing 5962-10237
- QML Q, QML V pending
INTRODUCTION
The UT16MX116/117 are low voltage analog multiplexers with
a convenient LVCMOS (3.3V) or CMOS digital interface set
by the voltage level of the VDD_IO pin. The analog muxes have
Break-Before-Make architecture with a low channel resistance.
The muxes support rail-to-rail input signal levels. The
multiplexer supports serial (SPI), or asynchronous parallel
interface.
The UT16MX116/117 operates with a single 5V(+10%) analog
power supply. An external 3.3V digital voltage supply is
required, for the digital circuitry. The digital I/O supply may be
set to 3.3V + 10% or 5V+ 10% by the VDD_IO pin.
Digital Interface Logic
Digital Interface Inputs
S[0]
S[1]
S[2]
S[15]
COM
Break-Before-Make
Architecture
...
4
Figure 1. UT16MX116/117 Block Diagram
Mixed-Signal Products
UT16MX116/117 Analog Multiplexer
Preliminary Data Sheet
January 25, 2011
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