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參數(shù)資料
| 型號(hào)： | 5962R9584502QXC |
| 英文描述： | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 1/41頁 |
| 文件大小： | 290K |
| 代理商： | 5962R9584502QXC |
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REVISIONS
LTR
DESCRIPTION
DATE (
YR-MO-DA
)
APPROVED
A
Add device types 04, 05, and 06. Modify boilerplate to include rad hard
requirements. Editorial changes throughout.
96-03-13
Monica L. Poelking
B
Add device types 07, 08, and 09. Update boilerplate. Editorial changes
throughout. – TVN
98-08-27
Monica L. Poelking
C
In table I, change I
IN
limits; add footnote to I
DDQ
; add t
c
in power-up master reset
timing section; add footnote to V
OS
and V
DIS
. Correct the JTAG timing waveforms.
Change footnote 3/ in table III. – TVN
99-04-28
Monica L. Poelking
D
Add device types 10 and 11. Editorial changes throughout. - TVN
00-06-27
Monica L. Poelking
E
Add notes to memory write and memory read waveforms. Editorial changes
throughout. – TVN
01-03-13
Thomas M. Hess
F
Correct dimension L for case outline Y in figure 1. Also, correct footnote 1/ for
radiation exposure connections in figure 6. – TVN
01-07-27
Thomas M. Hess
REV
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REV
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PMIC N/A
PREPARED BY
Thomas M. Hess
CHECKED BY
Thomas M. Hess
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
95-03-31
MICROCIRCUIT, DIGITAL, CMOS, SERIAL
MICROCODED MULTI-MODE INTELLIGENT TERMINAL
AND TRANSCEIVER, SILICON
SIZE
A
CAGE CODE
67268
5962-94663
STANDARD
MICROCIRCUIT
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
REVISION LEVEL
F
SHEET 1 OF 38
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E538-01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962R9584502QYC | x8 SRAM |
| 5962R9584502QZC | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 5962R9584502VUC | x8 SRAM |
| 5962R9584502VXC | 5-Pin, Multiple-Input, Programmable Reset ICs |
| 5962R9584502VYC | x8 SRAM |
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