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參數資料
| 型號： | 5962R9684502VXA |
| 元件分類： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封裝： | PGA-68 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
FEATURES
q 45ns and 55ns maximum address access time
q Asynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
q CMOS compatible inputs, TTL/CMOS compatible output
levels
q Three-state bidirectional data bus
q Low operating and standby current
q Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm2/mg
- Latchup immune (LET >100 MeV-cm2/mg)
q QML Q and QML V compliant part
q Packaging options:
- 68-lead Flatpack
- 68-pin PGA
q 5-volt operation
q Standard Microcircuit Drawing 5962-96845
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable ( OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
Figure 1. Logic Block Diagram
MEMORY
ARRAY
ROW
SELECT
ROW
SELECT
COL
SEL
COL
SEL
COLUMN
I/O
COLUMN
I/O
R/ WL
CE L
OEL
A11L
A10L
A9L
A0L
R/ WR
CE R
OER
A11R
A10R
A9R
A0R
I/O 7L
I/O 8L (7C139)
I/O7R
I/O8R (7C139)
I/O 0L
I/O0R
ARBITRATION
BUSYL
BUSY R
M/S
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