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參數(shù)資料
| 型號： | 5G64A-150M-FREQ |
| 廠商： | EUROQUARTZ LTD |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 1 MHz - 50 MHz, HCMOS/TTL OUTPUT |
| 封裝： | ROHS COMPLIANT, MINIATURE, SMD, 6 PIN |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 345K |
| 代理商： | 5G64A-150M-FREQ |
EURO QUARTZ
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 Email: info@euroquartz.co.uk www.euroquartz.co.uk
VCXO
11.4 x 9.6 x 4.7mm 6 pad SMD
G64 CMOS
DESCRIPTION
Frequency range 0.625MHz to 50.0MHz
CMOS/TTL Output
Supply Voltage 5.0 V or 3.3 VDC
Integrated Phase Jitter 1ps typical
PART NUMBERING
Example:
3 G64 B-80N-27.000
Supply Voltage
3 = +3.3V
5 = +5.0V
Series Designator
G64
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
G64 VCXOs, are packaged in a miniature 11.4mm x 9.6mm x 4.7mm
6 pad SMD package. Typical phase jitter for G series VCXOs is <1ps,
output CMOS/TTL. G series VCXOs use fundamental mode crystal
osccillators. Applications include phase lock loop, SONET/ATM, set-
top boxes, MPEG , audio/video modulation, video game consoles and
HDTV.
10Hz
-70dBc/Hz
100Hz
-105dBc/Hz
1kHz
-132dBc/Hz
10kHz
-142dBc/Hz
1MHz
-150dBc/Hz
Offset
Frequency 27.0MHz
PHASE NOISE
Frequency Range
Vdd = +3.3VDC:
0.625MHz to 50.0MHz
Vdd = +5.0VDC:
1.0MHz to 50.0MHz
Supply Voltage:
+3.3 VDC ±5% or +5.0VDC±5%
Output Logic:
TTL/HCMOS
Integrated Phase Jitter:
1.0ps maximum 12kHz to 20MHz
Period Jitter RMS:
2.0ps typical
Period Jitter Peak to Peak:
14ps maximum
Phase Noise:
See table below
Initial Frequency Accuracy
Tune to the nominal frequency with:
+3.3VDC:
Vc= 1.65V ±0.2V
+5.0 VDC:
Vc= 2.5V ±0.2V
Output Voltage HIGH (1):
90% Vdd minimum
Output Voltage LOW (0):
10% Vdd maximum
Control Voltage Centre
+3.3VDC:
1.65V
+5.0VDC:
2.5V
Control Voltage Range
+3.3VDC:
0.3V to 3.0V
+5.0VDC:
0.5V to 4.5V
Pulling Range
+3.3VDC
±80ppm to ±120ppm (standard)
+5.0VDC:
±80ppm to ±150ppm
(±200ppm available)
Temperature Stability:
See table
Output Load:
CMOS = 15pF, TTL = 2 gates
Start-up Time:
10ms maximum, 5ms typical
Duty Cycle:
50% ±5% measured at 50% Vdd
Rise/Fall Times:
0.7ns typical (15pF load)
Current Consumption:
10 to 45mA, frequency
dependent
Linearity:
10% maximum, 6% typical
Modulation Bandwidth:
10kHz minimum
Input Impedance:
1 MW minimum
Slope Polarity:
Monotonic and Positive. (An
(Transfer function)
increase of control voltage
always increases output
frequency.)
Storage Temperature:
-50° to +100°C
Ageing:
±5ppm per year maximum
RoHS Status:
Fully compliant
SPECIFICATION
Stability Code
FREQUENCY STABILITY
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
Stability ±ppm Temp. Range
OUTLINE & DIMENSIONS
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