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參數資料
| 型號： | 6273 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | 8-BIT LATCHED DMOS POWER DRIVER |
| 中文描述： | 8位鎖存DMOS功率驅動 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 172K |
| 代理商： | 6273 |
D
2
8-BIT LATCHED
DMOS POWER DRIVER
The A6273KA and A6273KLW combine eight (positive-edge-
triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microproces-
sor-based systems. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are
capable of sinking up to 750 mA. Similar devices with reduced r
DS(on)
will be available as the A6A273.
The A6273KA is furnished in a 20-pin dual in-line plastic package.
The A6273KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85
°
C.
FEATURES
I
50 V Minimum Output Clamp Voltage
I
250 mA Output Current (all outputs simultaneously)
I
1.3
Typical
r
DS(on)
I
Low Power Consumption
I
Replacements for TPIC6273N and TPIC6273DW
6273
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
Note that the A6273KA (DIP) and the A6273KLW
(SOIC) are electrically identical and share a com-
mon terminal number assignment.
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
IN
V
DD
GROUND
OUT
8
OUT
7
OUT
6
Dwg. PP-015-2
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
10
11
CLEAR
LOGIC
SUPPLY
STROBE
8
IN
7
IN
6
IN
5
IN
4
IN
3
IN
2
IN
1
Always order by complete part number:
Part Number
A6273KA
A6273KLW
Package
20-pin DIP
20-lead SOIC
R
θ
JA
55
°
C/W
70
°
C/W
R
θ
JC
25
°
C/W
17
°
C/W
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
Output Voltage, V
O
.............................
50 V
Output Drain Current,
Continuous, I
O
.......................
250 mA
*
Peak, I
OM
..............................
750 mA*
Peak, I
OM
.....................................
2.0 A
Single-Pulse Avalanche Energy,
E
AS
..............................................
75 mJ
Logic Supply Voltage, V
DD
................
7.0 V
Input Voltage Range,
V
I
.................................
-0.3 V to +7.0 V
Package Power Dissipation,
P
D
........................................
See Graph
Operating Temperature Range,
T
A
..............................
-40
°
C to +125
°
C
Storage Temperature Range,
T
S
..............................
-55
°
C to +150
°
C
* Each output, all outputs on.
Pulse duration
≤
100
μ
s, duty cycle
≤
2%.
Caution: These CMOS devices have input
static protection (Class 3) but are still
susceptible to damage if exposed to extremely
high static electrical charges.
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