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參數資料
| 型號： | 62C256 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數： | 6/8頁 |
| 文件大小： | 38K |
| 代理商： | 62C256 |
IS62C256
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-45 ns
Min.
-70ns
Symbol
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
Parameter
Max.
Min.
Max.
Unit
Write Cycle Time
45
—
70
—
ns
CS
to Write End
35
—
60
—
ns
Address Setup Time to Write End
25
—
60
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
25
—
55
—
ns
Data Setup to Write End
20
—
30
—
ns
Data Hold from Write End
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CS
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CS
Controlled,
OE
is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CS_WR1.eps
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