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參數資料
| 型號： | 658V3C2750M0000 |
| 廠商： | CTS CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 750 MHz, LVDS OUTPUT |
| 封裝： | GREEN, CERAMIC PACKAGE-6 |
| 文件頁數： | 2/5頁 |
| 文件大小： | 148K |
| 代理商： | 658V3C2750M0000 |
Document No. 008-0316-0
Page 2 - 5
Rev. A
CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108
Model 658
7x5mm Low Cost
LVCMOS, LVPECL or LVDS Clock
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Maximum Supply Voltage
VCC
-
-0.5
-
7.0
V
Storage Temperature
TSTG
-
-55
-
125
°C
Frequency Range
LVCMOS
50
-
250
LVPECL and LVDS
fO
-
38
-
750
MHz
Frequency Stability
(See Note 1 and Ordering Information)
f/fO
-
25, 50 or
100
± ppm
Operating Temperature
Commercial
0
70
Absolute
Maxi
m
u
m
s
Industrial
TA
-
-40
25
85
°C
Supply Voltage
(See Ordering Information)
VCC
± 5 %
2.38
3.14
2.5
3.3
2.63
3.47
V
Supply Current
Maximum Load
LVCMOS
< 160 MHz
≥ 160 MHz
-
40
50
LVPECL
< 160 MHz
≥ 160 MHz
-
75
100
LVDS
ICC
< 160 MHz
≥ 160 MHz
-
60
80
mA
Start Up Time
TS
Application of VCC
-
10
ms
Phase Jitter
tjms
Bandwidth 12 kHz - 20 MHz
-
3.5
5
ps RMS
Enable Function
Enable Input Voltage
VIH
Pin 1 or Pin 2 Logic '1', Output Enabled
0.7*VCC
-
V
Disable Input Voltage
VIL
Pin 1 or Pin 2 Logic '0', Output Disabled
-
0.3*VCC
Disable Current
IIL
Pin 1 or Pin 2 Logic '1' , Output Disabled
-
20
uA
Enable Time
TPLZ
Pin 1 or Pin 2 Logic '1'
-
5
10
ms
LVCMOS WAVEFORM
Output Load
CL
-
15
pF
Output Duty Cycle
SYM
@ 50% Level
45
-
55
%
Output Voltage Levels
Logic '1' Level
VOH
CMOS Load
90%VCC
-
Logic '0' Level
VOL
CMOS Load
-
10%VCC
V
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
-
2
5.0
ns
LVPECL WAVEFORM
Output Load
RL
-
50
-
Ohms
Output Duty Cycle
SYM
@ VCC - 1.3V
45
-
55
%
Output Voltage Levels
Logic '1' Level
VOH
PECL Load
VCC - 1.025V
-
Logic '0' Level
VOL
PECL Load
-
VCC - 1.62V
V
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
0.4
1.0
ns
LVDS WAVEFORM
Output Load
RL
-
100
-
Ohms
Output Duty Cycle
SYM
@ 1.25V
45
-
55
%
Differential Voltage
VOD
RL = 100 Ohms
250
350
450
mV
Output Voltage Levels
Logic '1' Level
VOH
LVDS Load
-
1.6
Logic '0' Level
VOL
LVDS Load
0.9
-
V
Elec
tric
al
and
Wa
ve
for
m
Pa
ram
ete
rs
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
-
0.4
1.0
ns
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging
at an average operating temperature of +40 °C.
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