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參數資料
| 型號： | 70824L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數： | 19/21頁 |
| 文件大小： | 191K |
| 代理商： | 70824L35PFI |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
7
Truth Table II: Sequential Read(1,2,3,6,8)
Truth Table I: Random Access Read and Write(1,2)
Truth Table III: Sequential Write(1,2,3,4,5,6,7,8)
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance.
2.
RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If
OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using
UB and LB separately are also allowed.
NOTES:
1.
H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2.
RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3.
CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the
sequential port operation (due to the counter and register control).
CMD should be HIGH (CMD = VIH) during sequential port access.
4.
SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge
of the clock during the cycle in which SR/
W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/
W or SCE is HIGH.
8. When
CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle
after Reset, Read (and write) Cycle".
Inputs/Outputs
MODE
CE
CMD
R/
W
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
L
HHL
L
DATAOUT
Read both Bytes.
L
HHL
L
H
DATAOUT
High-Z
Read lower Byte only.
L
HHL
H
L
High-Z
DATAOUT
Read upper Byte only.
LH
L
H(3)
LL
DATAIN
Write to both Bytes.
LH
L
H(3)
LH
DATAIN
High-Z
Write to lower Byte only.
LH
L
H(3)
H
L
High-Z
DATAIN
Write to upper Byte only.
H
X
High-Z
Both Bytes deselected and powered down.
L
H
X
High-Z
Outputs disabled but not powered down.
L
H
X
H
High-Z
Both Bytes deselected but not powered down.
HL
L
H(3)
L(4)
DATAIN
Write I/O0-I/O11 to the Buffer Command Register.
HL
L(4)
DATAOUT
Read contents of the Buffer Command Register
via I/O0-I/O12.
3099 tbl 11
Inputs/Outputs
MODE
SCLK
SCE
CNTEN
SR/
W
EOB1
EOB2
SOE
SI/O
↑
LL
H
LOW
LAST
L
[
EOB1]
Counter Advanced Sequential Read with
EOB1 reached.
↑
L
H
LAST
L
[
EOB1 - 1]
Non-Counter Advanced Sequential Read, without
EOB1 reached
↑
LL
H
LAST
LOW
L
[
EOB2]
Counter Advanced Sequential Read with
EOB2 reched.
↑
L
H
LAST
L
[
EOB2 - 1]
Non-Counter Advanced Sequential Read without
EOB2 reached
↑
L
H
LOW
H
High-Z
Counter Advanced Sequential Non-Read with
EOB1 and EOB2 reached
3099 tbl 12
Inputs/Outputs
MODE
SCLK
SCE
CNTEN
SR/
W
EOB1
EOB2
SOE
SI/O
↑
L
H
L
LAST
H
SI/OIN
Non-Counter Advanced Sequential Write, without
EOB1 or EOB2 reached.
↑
LL
L
LOW
H
SI/OIN
Counter Advanced Sequential Write with
EOB1 and EOB2 reached.
↑
H
X
LAST
X
High-Z
No Write or Read due to Sequential port Deselect. No counter advance.
↑
H
L
X
NEXT
X
High-Z
No Write or Read due to Sequential port Deselect. Counter does advance.
3099 tbl 13
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